Ali’s Status Report for 9/18

This week I spent most of my time trying to research new ideas for our project. I spent a lot of time trying to find new papers discussing the benefits of FPGAs while also looking through the papers Xiran and Grace sent, and trying to evaluate the feasibility of the ideas. On Wednesday we finally settled on an idea, and we realized that we have only used FPGAs where we were providing inputs in the design via the switches and buttons on the board. But, we wanted to be able to send data to the FPGA from the computer while still using an Altera FPGA. I found a paper which discussed the feasibility of using ethernet to send data from the computer (Data Transfer System for Host Computer and FPGA Communication) which assured us that our idea could be possible.

On Friday, the three of us met with Prof. Nace to discuss the feasibility of our idea a little more. He confirmed that we should be able to use the Altera FPGAs and that he thought our idea had some interesting applications.

Next week, I want to continue to investigate how to send data from the computer to the FPGA, and visa versa because this is our biggest bottleneck right now. Next week, we are hoping to decide on the best method to send/receive data, and also potentially speak with Prof. Hoe because his research area is related to our project.

Xiran’s Status Report for 9/18

I spent the majority of this week continuing to brainstorm project ideas. I looked into papers describing image processing and AI acceleration on FPGAs, before we settled on our idea on Wednesday. I then searched online and found many sources describing similar ideas (e.g., FPGA based accelerator for functional simulation, FPGA-accelerated evaluation and verification of RTL designs), which helped us confirm the validity of the use case and solution.

On Friday, I, along with my teammates, met with Prof. Bill Nace to discuss this idea further. I also set up the website. This weekend, I will help make the proposal slides. I am on schedule to meeting deliverables.

Next week, I will research communication protocols to send data to and obtain data from the FPGA. We should settle on one feasible protocol and begin implementing/benchmarking it.