This week I ran into quite a few issues which I was able to resolve for the most part. I started off the week by continuing to try to run the BIST (built-in self-test mentioned last week) by reading through the documentation and trying to find a Vivado project that I could program to the board. However, I ran into IP issues and decided to forgo running the BIST and simply create a project that would allow me to test out the UART capabilities of the FPGA.
I started off by reading the forums to try and find existing projects that would allow us to use the UART protocol on the board and came across the AXI UARTLite IP block that allowed me to configure the baud rate and protocol. There was an example project for the IP block, which I decided to try. After fixing a multitude of issues such as licensing issues, driver issues, and compilation issues (Note: One of the compilation issues involved making non-recommended changes to the provided XDC constraints file, which I am looking into), I was finally able to transmit a character from the board to the host computer. After completing this, I wrote a Python snippet using the PySerial library that was able to listen to the appropriate COM port and receive the transmitted character.
In terms of schedule, I am on track. My goal for the past week was to finish the implementation of the communication logic but I realized that the logic is tied together with the RTL code for the implementation of the joints algorithm and so, decided to instead start working on next week’s task which involves learning about HLS.