Posted on

Venkata’s Status Report for 10/10/20

This week I ran into quite a few issues which I was able to resolve for the most part. I started off the week by continuing to try to run the BIST (built-in self-test mentioned last week) by reading through the documentation and trying to find a Vivado project that I could program to the board. However, I ran into IP issues and decided to forgo running the BIST and simply create a project that would allow me to test out the UART capabilities of the FPGA.

I started off by reading the forums to try and find existing projects that would allow us to use the UART protocol on the board and came across the AXI UARTLite IP block that allowed me to configure the baud rate and protocol. There was an example project for the IP block, which I decided to try. After fixing a multitude of issues such as licensing issues, driver issues, and compilation issues (Note: One of the compilation issues involved making non-recommended changes to the provided XDC constraints file, which I am looking into), I was finally able to transmit a character from the board to the host computer. After completing this, I wrote a Python snippet using the PySerial library that was able to listen to the appropriate COM port and receive the transmitted character.

In terms of schedule, I am on track. My goal for the past week was to finish the implementation of the communication logic but I realized that the logic is tied together with the RTL code for the implementation of the joints algorithm and so, decided to instead start working on next week’s task which involves learning about HLS.

Posted on

Vishal’s Status Report for 10/2/20

This week, I was able to accomplish a few things towards the completion of our capstone project. I started off with my most important task which was to design the UI Model. I started off with simple sketches for multiple scenarios. These scenarios included the home screen, choosing the difficulties and different types of focuses for the workout as well as designing the actual pages for when the workouts were taking place. I tried to solidify these and refine them compared to what was presented in the proposal but the final version will be dependent on. I also begin the basic pygame framework and have it setup on my laptop. I will need to further refine this to be applicable to our design as well as our project. I would like to make more progress with the pygame application as we do not have our webcam yet so I was not able to test out the image capture process fully. I have been working with the laptop webcam to see if the same scenario is feasible for capturing and displaying video. I will have to do a bit more testing to integrate that with pygame and see if multi-threading is feasible with pygame. In terms of my progress I am a little bit behind right now but I don’t see that being a problem because the schedule has a bit of slack for me. My plan for next week is to fully integrate the video feed with the pygame application and have images be captured periodically. I will also be trying to integrate recorded videos into the pygame application.

Posted on

Team Status Update for 10/2/20

We looked through the feedback provided by our peers for our proposal presentation. As of now, there are no major changes to the project in terms of the design and the schedule. One thing that we discuss was whether we should market our project as more of a platform/framework rather than a final product to justify our design choices. We will continue to discuss this idea and see if there are any changes to made to the overall design of the project. In the meantime, we were able to finalize all of the parts that we need and have placed orders for the parts that could be a hindrance in the near future.

Posted on

Venkata’s Status Update for 10/2/20

This week was predominantly focused on set up and research related tasks. In terms of set-up tasks, I set up the website for the rest of the team and also picked up the Kintex-7 FPGA board from the Academic Center. In terms of the research related tasks, the primary goal of the past week was to learn the UART communication protocol. I was able to familiarize myself with the protocol and be able to understand how the FPGA and the host computer will interact with one another. I was able to find code snippets that use the python library pySerial to transmit data from a computer port with UART. On the other hand, I was also able to find Verilog code snippets that resemble a UART transmitter and receiver. So, I was able to finish the task for learning the protocol.

However, this week was also allocated for beginning to implement the logic. In order to do so, I tried to run the BIST (built-in self-test) on the Kintex-7 board but am currently running into issues because the board doesn’t appear to be transmitting the expected data to the host computer. Furthermore, programming the board requires Vivado, which is not available on MacOS, so I had to partition my MacBook and install bootcamp before I could install Vivado. For the upcoming week, I plan on resolving the issues and being able to successfully run the BIST and running through the UART option that is present. After which, I plan on finishing the implementation of the logic to communicate between the board and computer, which will allow me to stay on task with the schedule.