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Jared’s Status Report for Apr 11

After meeting with a professor, I have determined that the SPI clock cannot run as fast as I expected. However, SPI is still the fastest method to transfer data.

What has changed is that the SPI clock will run at 15.6 MHz, or 250MHz / 16. This means that the 50MHz FPGA clock can successfully process the SPI clock without relying on a separate clock. I still have to code this, but it will be done by Monday.

By Friday, I plan to finish all of the SPI bus and spend the weekend completing additional tasks for TJ.

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Mark’s Status Report for April 11th

This week, I wrote a helper function that takes a ML model and returns a list of all the layers of that model in the order that they are called in. This took longer than expected as some layers were not showing up properly or in the right order. Additionally, I had to make some small modifications to the serialization of the models since we made some changes to the Transport Layer Protocol. The two changes were changing the size of each packet of information (from any size -> 4 bytes), and swapping the order of the preambles before sending each layer.

This coming week, I plan on finishing up the serialization of a specific model, and then checking that every model that was defined in the benchmark.py file serializes correctly.

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Team Status Report for April 11

Accomplishments

TJ has completed the following FPU operations:

Operation Described? Implemented? Testbench?
Linear Forward Yes Yes Yes
Linear Backward Yes Yes
Linear Weight Gradient Yes Yes
Linear Bias Gradient Yes Yes
Convolution Forward Yes
Convolution Backward Yes Yes
Convolution Weight Gradient Yes
Convolution Bias Gradient Yes
MaxPool Forward Yes
MaxPool Backward
ReLU Forward Yes
ReLU Backward Yes
Softmax Forward
Softmax Backward
Cross-Entropy Backward
Flatten Forward Yes
Flatten Backward Yes Yes
Parameter Update Yes  

 

And will be finishing the rest to get an end-to-end test working.

Mark has finished the helper function to sort through a model and list out every layer that is called in the specific order. This will be used in order to serialize each model. Mark also made small changes to the Transport Layer Protocol.

Jared has fixed bugs in the SPI protocol and guaranteed its ability to function on the RPi.

Schedule

TJ will spend the next week finishing up the FPU Job Manager and implementing the rest of the Model Manager in preparation for the Demo on Monday.

Mark will spend the next week making sure that models are being serialized over correctly.

Jared will complete the SPI bus implementation, along with additional processing for data receiving.

 

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Theodor’s Status Report for April 11

Accomplishments

This week I’ve been working on the FPU Job Manager Operations. I’ve been following my previous process of describing the FSM control signals state-by-state, then simply copying them over into SystemVerilog. Here’s what I have so far:

Operation Described? Implemented? Testbench?
Linear Forward Yes Yes Yes
Linear Backward Yes Yes
Linear Weight Gradient Yes Yes
Linear Bias Gradient Yes Yes
Convolution Forward Yes
Convolution Backward Yes Yes
Convolution Weight Gradient Yes
Convolution Bias Gradient Yes
MaxPool Forward Yes
MaxPool Backward
ReLU Forward Yes
ReLU Backward Yes
Softmax Forward
Softmax Backward
Cross-Entropy Backward
Flatten Forward Yes
Flatten Backward Yes Yes
Parameter Update Yes

Last week, I had the Convolutional Forward and Linear Forward operations described, and only the Linear Forward operation implemented.

I’ve consolidated all of the weight and bias operations into a single “Parameter Update” operation, since they’re all the exact same and the shape of each tensor can be read from memory.

Another work-around I’m implementing is for the Softmax Backward operation. I haven’t been able to find a working floating-point exponent calculator in Verilog, so in the case that I’m unable to find one, I will simply subtract the output from the label, which in terms of optimization will have the same effect as taking the backwards gradient of the softmax direction.

Schedule & Accomplishments for Next Weeks

I’ll be finishing up the FPU Job Manager operations over the next couple days, then preparing the Model Manager for the Demo.

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Jared’s Status Report for April 4

Placing the program on the FPGA isn’t as easy as I thought it would be.

Things that were easy:

  • Following the user manual and learning pin assignments
  • writing a compliant SPI module

Things that are hard:

  • Deciphering the signals from the RPi
  • Receiving the signals correctly

Here is my current configuration for the physical board:

Followed by a screenshot in Quartus of the interface (while debugging):

The SPI module likes to act strange: Once in a while it will count too many clock cycles and receive or return a bad buffer. This doesn’t appear when connecting MISO and MOSI together (loopback), so it must be with the Pi.

I have contacted sources outside the group for help, as without an oscilloscope I don’t think I can properly assess my issue.

Next week will be dedicated to getting SPI working.

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Mark’s Status Report for April 5

This week, I finished the tensor serializer helper function for serializing tensors between 1-4 dimensions. This meant converting any of the various dimensioned tensors into a single dimension list based off of the Transport Protocol that we had described previously. Additionally, I wrote a basic serialization for each of the six possible layers that a model could have (Linear, 2D Convolution, ReLU, Maxpool2D, Flatten, Softmax). As of this point, all tensors use integer values to represent values as it is easier to validate a tensor is being serialized correctly.

This coming week. I plan on fully implementing the serialization for each of the six possible layers, as well as cleaning up the interaction between the Data Source machine and the Worker.

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Theodor’s Status Report for April 4

Accomplishments

This week, I started building the FPU Job Manager and implemented the Linear Forward operation. For the interim demo, I constructed a testbench that computes a matrix-vector multiplication using the FPU Job Manager.

Schedule

No schedule changes are needed for next week. I will continue implementing FPU Job Manager operations.

Accomplishments for Next Week

Next week I will have Convolutional forward implemented and the FSM Control signals defined for the rest of the operations we plan to implement.

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Team Status Report for April 4

Accomplishments

 

Theodor implemented the skeleton of the FPU and implemented the Linear Forward Operation. He also implemented the assignment phase of the Model Manager.

Mark implemented the Tensor serializer (Dimensions 1-4) as well as a rough skeleton for serializing each of the various layers of a model.

Jared implemented a UDP client for the Raspberry Pi and is debugging the SPI protocol on the FPGA.

Schedule

 

Accomplishments for next week

Theodor will spend next week implementing the rest of the FPU Job Manager operations. After that, he will finish work on the Model Manager and (if necessary) implement the DPR for end-to-end communication.

Mark will spend next week implementing the serialization of each of the potential layers, as well as cleaning up the communication between the Data Source machine and the Rasp Pis.

Jared will produce a working SPI implementation and a receiving module for the FPGA. This includes correct interpretation of the transport layer protocol.

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Mark’s Status Report for March 28

This week, I set up a basic framework for the Worker Finder using the UDP communications protocol. I tested this feature by setting up a server and sent messages back and forth between the Worker finder and the server. The server in this case acts as a Rasp Pi. There is still a little bit of work left to do on the Worker Finder as I am unclear about some of the very specific details of the implementation. This coming week, I plan on working with Jared to hash out these details as he in charge of the Bus Protocol.  I also plan on working on the Workload Manager, specifically using the third party tool that I found a couple weeks back to measure the size of a model given the input parameters.

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Jared’s Status Report for Mar. 28

This week I wrote an initial draft of the SPI slave SystemVerilog code. Todo is the code to faciliate data transfer betwenn the Ethernet and SPI. This should meet the mark where we can put our pieces together, however I would still need to write some tests.

I received the parts for the setup this week. I will be connecting them to the host desktop for us to use and test on.

In relation to TJ I have been slacking a bit on code. I hope to meet with him once this section is done and work on the meat and bones of the project a bit more.