Project Progress Summary
This week, our team focused heavily on preparing for the design review presentation. We synthesized our progress into a cohesive presentation covering our design requirements, solution approach, and implementation plan. Additionally, we continued independent work on the hardware implementation of the Ricoh 2A03 and 2C02 components to ensure our cycle-accurate goals remain on track.
Risk Management and Schedule
The most significant risk remains meeting the strict timing requirement within our Verilog design to achieve cycle-accurate recreation. As we detailed in the previous week, this can only be fully verified once the CPU design is complete and we perform a formal timing analysis. We are currently managing this risk by adhering to a modular design approach, allowing us to isolate and optimize critical paths early in the implementation phase.
We have made some changes to our design of the multiplayer sync part. Instead of only sending status packets to the second FPGA which only contains the PPU unit, we decide to have the two FPGAs synthesized with exactly the same hardware running the same game simultaneously, and only sync the inputs from the gamepad. Our project remains on schedule. We expect to begin more intensive testing of the custom network synchronization layer once the individual CPU and PPU modules reach their next implementation milestones.