This week, a significant portion of my time was dedicated to the design review presentation. I wrote about our design requirements and the solution approach for the hardware recreation. Regarding hardware implementation, I made progress on the 6502 instruction set logic. Building on last week’s work with bytecode conversion, I have begun writing the RTL for the core execution unit. I have also started setting up the Implementation and Testing plans to verify that our timing remains deterministic as we integrate the CPU with the memory mapping unit.
My progress is currently on schedule. While the Design Review required significant documentation effort, I have maintained the pace for the CPU implementation phase. For the upcoming week, I aim to finalize the initial RTL for the Ricoh 2A03 core instruction set, and run the full suite of assembly tests through the VCS test bench to ensure functional correctness.