Mihail’s Status Report for 03/14

A substantial portion of my time this week was spent on the personal portion of the ethics assignment. With my remaining time, I began implementing the FIR filter component. To design the filter, I parameterized the RTL so that an arbitrary number of prior samples x[n−i] could be stored in on-board BRAM. I then used the param_registers, modules I created last week to store the filter coefficients b_i. The combinational logic reads each stored sample x[n−i] along with its corresponding coefficient bi, and multiplies the pair using a DSP slice. This approach is similar to the one used in the delay component; I found that the design effort saved by leveraging DSP slices outweighed the cost in DSP resources. The intermediate products are then accumulated using an adder tree, so that summing N samples requires ceil(log2(N)) stages of addition. In order to write the values into BRAM, I maintained a circular pointer into memory that updated every cycle, as with the delay component. Additionally, I enabled pipelining on the adder tree, in case there was significant combinational delay in the component.