After working on the individual ethics assignment, I spent the week further debugging and working on planning out the audio codec’s integration with the overall signal generation pipeline. I investigated the possibility of using external IP for generating a PLL (Phase Locked Loop) for the I2S portion of the interface, since further research showed that there was a need for having a stable clock. The protocol needs to operate at a 12.288 MHz clock, yet the input signal I am currently using is the DE10-Standard’s general 50 MHz clock. Currently, we are using a free version of Quartus for managing our FPGA, so I was worried that it wouldn’t be available to us.
After working on this, I spent some time discussing with Kaloyan on how we would be integrating the signal generation system. We realized pretty quickly that it would involve dealing with clock domain crossing, as our overall system would most definitely be running at a different speed to the 12.288 MHz for communicating with the I2S module. The original plan was to stream each value from the generated signal through a FIFO, so we chose to keep that same idea and use an asynchronous FIFO. The writing side for it will run at 50 MHz (the clock speed for the overall system), while the read side runs at the I2S interface’s 12.288MHz. While I wrote the RTL for the system this week, I plan to work on testing it the following week (and trying to get some integration going on). Everything is still in progress, thanks to the fact that we had moved getting keyboard input to work back.
Overall, the system now has the updated setup:
