This week didn’t bring us any new risks. In order to minimize risk we worked on debugging the RTL, coding up our interface between the DSKY micro-controller and the AGC CPU, and writing the AGC assembly code.
We have no new big changes to our schedule this week. We are on schedule in the terms of RTL and ahead of schedule in the terms of DSKY work.
There has been progress on the AGC code to be run on our architecture. We have verified that all the math functions were in working order and the simulations were accurate. Therefore, we will soon begin installing Linux on the FPGA SoC core and attempt AXI communication with the FPGA. This step is important for the demo and the AGC programs as we have to be aware of the AXI’s functionalities and limitations, which could be of moderate risk.