I spent most of this week debugging as much as I could wile waiting for my partner to finish his portion of the RTL. I compiled the finished portion of the RTL and caught a few bigger conceptual bugs that our pipeline previously had. One example of this is a bug where we had hardwired the bank registers to the memory addressing unit so it would know which bank to address into. The issue with this is since we are pipe-lining we need the relevant banks for reading (which takes place in decode stage) and writing (which takes place in writeback stage) and these might be two different values. To fix this we had to split our adresing unit and have our bank bits be forwarded throughout the pipeline. I also figured our how we will compile our SystemVerilog files (harder than I thought because I’m used to makefiles doing it for me).
I am ahead of schedule. However as I have had more time the last couple of weeks compared to future weeks so this is kinda expected. Next week I hope to get the pipeline working and running the tests without failing. However I still think this is ambitious and this goal is not entirely dependent on me (waiting for my partners to finish their RTL).