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Team Status Report 4/30

The risk we worked on mitigating this week was not being able to effectively present our work. This week we finished up the presentation slides, and gave the presentation. In addition we made the poster and made a lot of the material for the video.

The video is being edited in Adobe After Effects, with elegant animations and transitions in an attempt to make the material as digestible as possible. Although very manually labor intensive, it provides professional visuals which will accompany our project.

We are done the presentation and the poster. Next week we will focus on updating the design report into the final report. We will also record and finish editing the final demo video. Lastly, we will attend the Tech spark Design Expo and final demo exhibitions.

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Christopher’s Status Report 4/30

My task for this week was finishing the presentation, making the poster, and helping with the video. During the weekend (Sunday) I edited and polished the slides before we turned them in. I also held sole responsibility for the poster. So I made that. Lastly I helped with the video by making editing and polishing the diagrams relevant to the part of the project I implemented. I created or edited the memory map diagram, the ISA table, the pipeline diagram, and the tool chain diagram. Lastly I worked with Donny to write the script for the part of the videos which were relevant to the part of the project in which I worked on. We are on schedule with the poster finished and the video well under way. Next week I will be working apple video and the final report and demoing and presenting to the public.

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Team Status Report 4/23

The main risk we mitigated was not having a demo-able project. This week we finished integration between the FPGA AGC and the DSKY and ESP along with our laptop display. We then debugged our demo program on our working implementation or our project. It now works, the preliminary demos for escape velocity, orbital transfers (Hohmann Transfer), and Translunar injection have been verified to be correct using our custom 3-body simulator.

We also worked on the presentation this week also (as the presentation in next week) working on this entailed taking various metrics from our design such as the operating temperature of our DSKY the IPC of our AGC implementation and many other metrics. We then used this to make the presentation.

We are ahead of schedule now that we are done with the technical aspects of our project. Next week we will focus on the final report, poster, and demo video.

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Christopher’s Status Report 4/23

My task for this week was integration and making the presentation. As far as integration went I was responsible for making sure the uart connection and io interface between our FPGA implementation of the AGC and the microcontroller worked (mostly on the FPGA side) and spend several hours debugging that. I also helped Jae with debugging the demo code once it was running on everything. Lastly I organized the work for the presentation and made several slides. To work on the presentation (particularly the  quantitative testing slides) I had to write some code and take benchmarks of our design. We are more or less done with the technical component of our project (a week ahead of schedule). Next week I will be working on the poster and the apple video and the final report and whatever else we need to finish up the project.

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Team Status Report 4/16

One risk we mitigated this week was incorrect behavior with double word instructions (MP and DDOUBL). We got multiply working by running it on our testing suite in simulation then reading the waveform. We also worked on our I/O unit, specifically with UART interface logic, to minimize risk as we move into the high-level integration of our entire system next week.

We were able to fully test and verify in hardware the workings of UART TX (Transmission of data from FPGA AGC to DSKY) through using both an oscilloscope and via an FTDI UART to USB converter. We are still working on RX. We plan completing full integration next week.

We have no new big changes to our schedule this week. We are on schedule in the terms of RTL and ahead of schedule in the terms of DSKY work

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Christopher’s Status Report 4/16

My task for this week was sharing synthesizing the design on the chip with Donny. However due to Donny being behind I ended up writing the parent module and the transmit module of the IO unit for Donny. I also synthesize the design and made the fixes necessary by myself. However since Donny was not done with the receiving module as of the writing of this I could not synthesize the entire design (basically was just missing the receiving module). Even though we are technically slightly behind (could not synthesize) hopefully we will finish that in our meeting today. Our plan for next week is integration. None of use really have a specific task because we will all be there to help debug our prospective bugs if any come up during that. In addition we should probably make the slides for the final presentation which I believe is in 2 weeks (we will likely each claim a few slides for that)

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Team Status Report 4/9

This week a new risk is that we are having trouble with double word instructions (MP and DDOUBL). If we cannot get those working we could be in trouble. In order to minimize risk we worked on debugging the RTL by running it on our double word instruction tests. Other things we are doing to minimize the risk of our project not working is coding up our interface between the DSKY micro-controller and the AGC CPU, and writing the AGC assembly code. The AGC CPU is therefore in the testing and verification phase, and we will begin full integration with the DSKY hardware soon, as well as the AGC demo programs.

We have no new big changes to our schedule this week. We are on schedule in the terms of RTL and ahead of schedule in the terms of DSKY work.

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Christopher’s Status Report 4/9

I spent most of this week debugging the RTL. I got the rest of the test cases working this week and helped debug Jae’s code when it was running on the RTL simulation. I also changed the pipeline to support an instruction we did not previously think we were gonna use (DDOUBL). Next week I hope to start synthesizing our code and help Jae with any more debugging. I am on schedule but I doubt I will be able to do everything I need to do next week because of a dependency on Donny.

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Team Status Report 4/2

This week didn’t bring us any new risks. In order to minimize risk we worked on debugging the RTL by running it on our custom test cases, coding up our interface between the DSKY micro-controller and the AGC CPU, and writing the AGC assembly code. The AGC CPU is therefore in the testing and verification phase, and we will begin full integration with the DSKY hardware soon, as well as the AGC demo programs.

We have no new big changes to our schedule this week. We are on schedule in the terms of RTL and ahead of schedule in the terms of DSKY work. The DSKY firmware will be fully complete by next week and the AGC demo programs will start to take shape.

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Christopher’s Status Report 4/2

I spent most of this week debugging the RTL. I compiled the finished portion of the RTL and resolved all the lint issues with my portion of the code. I then traced through the most basic test case I wrote INCR.agc. This test case branched then incremented a few addresses in memory before ending. Getting this test case to work required me to catch several bugs. One with the reset value of the pipeline registers, one with reading from ROM, a couple misconceptions in the addressing unit and in the pipeline and some issues in the decoder. According to the schedule Donny and I have one more week till we pass all the test cases. We are on schedule but need to stay work hard next week to stay on schedule.