One risk we mitigated this week was incorrect behavior with double word instructions (MP and DDOUBL). We got multiply working by running it on our testing suite in simulation then reading the waveform. We also worked on our I/O unit, specifically with UART interface logic, to minimize risk as we move into the high-level integration of our entire system next week.
We were able to fully test and verify in hardware the workings of UART TX (Transmission of data from FPGA AGC to DSKY) through using both an oscilloscope and via an FTDI UART to USB converter. We are still working on RX. We plan completing full integration next week.
We have no new big changes to our schedule this week. We are on schedule in the terms of RTL and ahead of schedule in the terms of DSKY work