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Team Status Report for (2/27/2021)

This week, we had finalized our project proposal presentation as well as all the components that went into it. The planning aspect has helped us greatly so that we can see how we are progressing and how quickly we must progress to meet our deadlines. Also the project block diagram has made sure that all team members are on the same page on how integration will work and clarifies what exactly we are working on.

Drew and Joseph have set up their environments to begin work with openCV and Michael has set up his environment to work with the FPGA. All members have begun writing some code to either test out the modules and libraries they are using or to sketch out their code and plans.

We have ordered all the basic components which are needed for the computer vision aspect of the project and a github repository has been created so that we can collaborate on this aspect of the project easily.

All team members have gotten their environments setup and will begin implementation in the coming weeks as scheduled in our Gantt chart. Hence, everyone is on schedule and have met their goals for this week.

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Michael Status Report for 2/27/2021

This week, after finishing the project proposal slides with my teammates, I have begun working on the system verilog implementation of the chess game logic. I have begun sketching out a high-level block diagram for how I want to represent pieces in my system and how I want to implement something such a packet to send via UART. I have a very rough SV module currently that roughly implements the board state as a 64-word register. This will act as my starter code for the rest of the deliverables.

I have also begun to set up my environment. I have installed Quartus Prime lite on my computer and have begun reading the documentation for the UART IP block which comes with Quartus. My main challenge for next week is implementing a basic module which sends and receives basic packets from my computer. I will also formally request an FPGA from the ECE department. After reviewing the list of available FPGAs I will likely request a DE-10 Standard Dev kit and a UART to USB cable as this is the FPGA that I am most familiar with.

I am currently on schedule with the Gantt chart and scheduling plans we had agreed on in our project proposal.

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Team Status Report for 02/20/2021

Thanks to the advice from the professor and the TA, we could finalize our team project’s direction. We were considering using a customized LED board, but we realized that all the work to solder LED on a Chessboard is not worth it. Rather, we chose to use a monitor screen to show the moves of an AI and a user. This way, we believe that our overall project will be more concise and value more on the part of the project that is more crucial. Furthermore, using a monitor will make debugging much easier than using a customized LED board. A monitor will clearly show an update of the board which we can easily track down the progress as the board gets updated. After we have finalized the route of our project, we listed down and divided the tasks that are required for the project. As we broke down the components, we could grasp a rough timeline of how we should progress our Capstone project. Besides, we all contributed to making a proposal presentation which is coming up next week. We are looking forward to our proposal presentation.

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Michael’s Status Report for 2/20/2021

This week was focused on setting up and finalizing our project proposal. This week I have worked on the slides which are set to be completed by tomorrow 2/20/2021. We decided to keep most of the game logic and legal move calculation/generation within the FPGA because it is most easily parallelizable on the FPGA and my knowledge in the field enables us to take advantage of this.

I have also begun researching various variables to decide what FPGA would be needed to make the system. The UART module should be an IP block, so I have been looking at what system (Xillinx vs Altera) provides a more robust UART IP block. Currently I am leaning towards an Xillinx system, but that would entail also learning the Vivado toolchain, although I have done some High-level synthesis within Vivado in the past.

Next week I hope to finalize this and request an FPGA from the ECE department and begin working on setting up the UART communication. I would also like to start some Verilog hacking to begin the initial game logic (not pipelined).