This week was focused on setting up and finalizing our project proposal. This week I have worked on the slides which are set to be completed by tomorrow 2/20/2021. We decided to keep most of the game logic and legal move calculation/generation within the FPGA because it is most easily parallelizable on the FPGA and my knowledge in the field enables us to take advantage of this.
I have also begun researching various variables to decide what FPGA would be needed to make the system. The UART module should be an IP block, so I have been looking at what system (Xillinx vs Altera) provides a more robust UART IP block. Currently I am leaning towards an Xillinx system, but that would entail also learning the Vivado toolchain, although I have done some High-level synthesis within Vivado in the past.
Next week I hope to finalize this and request an FPGA from the ECE department and begin working on setting up the UART communication. I would also like to start some Verilog hacking to begin the initial game logic (not pipelined).