This week, after finishing the project proposal slides with my teammates, I have begun working on the system verilog implementation of the chess game logic. I have begun sketching out a high-level block diagram for how I want to represent pieces in my system and how I want to implement something such a packet to send via UART. I have a very rough SV module currently that roughly implements the board state as a 64-word register. This will act as my starter code for the rest of the deliverables.
I have also begun to set up my environment. I have installed Quartus Prime lite on my computer and have begun reading the documentation for the UART IP block which comes with Quartus. My main challenge for next week is implementing a basic module which sends and receives basic packets from my computer. I will also formally request an FPGA from the ECE department. After reviewing the list of available FPGAs I will likely request a DE-10 Standard Dev kit and a UART to USB cable as this is the FPGA that I am most familiar with.
I am currently on schedule with the Gantt chart and scheduling plans we had agreed on in our project proposal.