This week the goal was to set up everything for integration. Adolfo and Tess started moving the simulation CPU onto the FPGA. Unfortunately, they thought that combinational read memory would be available. Tess focused on finding a work around and updating the logic to match. She was able to solve this issue by using a faster clock for memory. Since synthesis takes a long time for such a large project, she updated the simulation model to match what the FPGA would look like.
Since the CPU is essentially done for games that only use ROM0, Tess moved onto implementing a memory bank controller (MBC) so the emulator could support more games. This required creating a controller that controlled memory accesses to a different memory location so the CPU was hidden from the difference.
Adolfo focused on finishing and then perfecting the PPU. Since last week, he polished implementing scroll and fully implemented and tested sprites. Although the PPU was already passing more tests than other emulators, but his goal was to pass almost all of them to clearly pass our expectations. He had to refine his logic because of the timing and memory change, but then he worked on perfecting the display. He is debugging a test that displays a face because it is a hard test that specifically targets all the small details of the PPU.
Additionally, Adolfo set up the registers on the FPGA side to accept joypad inputs. He is now working with Pratyusha to get the SoC to write to those registers.
By tomorrow’s demo, they hope to have Tetris running on the FPGA.
This week, Pratyusha had two objectives –
- To get the USB Controller driver working
- To get the SDRAM Nios-2 test running on the board
For 1. Pratyusha compiled modules with an unofficial version of the linux kernel with special flags, and ported over drivers to the board, which after configuration could receive bytes from the controller. For the NES-controller’s controller, she understood the event structures, types and linux/input.h, details linked here, and then composed code to handle multiple presses and releases of the controller inputs, and dealt with variable length packets.
All in all, the end result is as shown here. Each button press and release maps to the respective led being on and off.
2. Additionally, Pratyusha got the SDRAM NIOS-2 test to work on the FPGA board. This means we can copy over information to the SDRAM from the SoC, and read back from it and compare the bytes, to check if they are the same. Still have to implement checking the sums being equal for the bytes on FPGA and SoC.
Goal for this week is to read from USB storage, and write those bytes to SDRAM, read them back and store it on the USB flash.