This week was about experimenting with the GPIO bus protocol, understanding shortcomings and learning about specialized hardware withing the Pi.
Accomplishments
I’ve started on some final documentation for the bus protocol. Initially there was pressure (at least from myself) to prioritize throughput. That hasn’t changed, but after some research on optimum speeds for GPIO, some decisions had to be made to make life simpler down the chain.
The custom bus protocol we earlier designed is likely being scrapped for the built-in SPI protocol. There are a few factors involved:
1. The custom protocol was clock agnostic, in which data was sent parallel with an activating bit. SPI, while not having built-in parallel data, may still have GPIO toggling transfer modes.
2. The optimum throughput rate was a best guess given throughput benchmarks from StackOverflow that may not properly reflect setting multiple GPIO. With the Pi’s SPI clock at a maximum rate of 125 MHz, a more reliable and debuggable interface will help in the future.
Schedule
This week, I need to write a program for the SPI interface and a test module to run on an FPGA. By Friday, the module needs to be done and tested.