Accomplishments
This week, I’ve finished up the documentation that describes handshakes between different hardware modules. At this point, the hardware modules are defined well enough that the work can be divided among multiple people and they can be developed independently.
Importantly, the handshakes I defined were:
- Data Pipeline Router <-> Model Manager
- Floating Point Bank <-> Model Manager
This does sound small compared to what I accomplished last week, but defining how these two modules interact will allow us to completely separate the tasks of implementing the major modules in Hardware.
I’ve also done research on the SystemVerilog shortreal data type, which is effectively the same as a float in C. Having this will make it very easy to implement most floating-point operations in hardware, especially since they will be combinational. However, I still need to do more research on the footprint of default synthesized floating-point circuits.
Schedule
Next week, I really need to get started on implementing some of the smaller modules like the Job Manager and M9K/SDRAM interfaces. These are essential components and are defined well enough that they will not be changing for the rest of the project.
Accomplishments for Next Week
Almost all of the questions related to hardware have now been answered, but implementation, for the most part, has not started yet. It is essential that this start soon, especially with the midway demo happening in Week 11.