Felipe Perotti’s Status Report for 10/03/2026

Progress This Week

This week I was focused on the communication protocols we will use for transmission between the ADC and the ESP32 as well as from the ESP32 to the final end point device.

This week I focused on the communication protocols that will support data transmission between the ADS1299 ADC and the ESP32, as well as between the ESP32 signal-processing board and the final endpoint device.

Initial findings indicate that the system should be treated as two separate communication links. The ADS1299-to-ESP32 connection requires a deterministic, low-latency interface—most likely SPI—with careful synchronization using the data-ready signal. This link must preserve sample timing and prevent data loss during continuous EEG acquisition.

The ESP32-to-endpoint connection will require a balance between latency, bandwidth, range, power consumption, and reliability. Candidate interfaces include Bluetooth Low Energy, Wi-Fi, or a wired UART/USB connection, depending on the final endpoint requirements. Regardless of the selected technology, the transmitted data should include packet framing, sequence numbers, timestamps, signal samples, status information, and error checking.

The main communication risks identified so far are packet loss, timing jitter, synchronization errors, and increased latency. These factors could affect the quality and real-time performance of the BCI system. The next step is to benchmark the candidate protocols using end-to-end latency, packet-loss rate, throughput, and system resource usage as the primary evaluation criteria.

I also began 3D Printing the headset but have yet to find good files for spring mechanisms to keep tension  between electrodes and head. Will report further next week.

Next Week

For next week I plan on finishing the needs for the headset and to start identifying the low level software we’ll need for communication.

Schedule

I am on schedule.

Atharv Kashyap’s Status Report for 10/03/2026

Atharv Kashyap‘s Status Report for 10/03/2026

This week I moved from planning the signal-processing pipeline to building it. I implemented the first Python version of the SynapSys decoder, including bandpass/notch filtering, CCA, three-command classification, and rejection logic. I kept the main parameters configurable so we can easily change things like sample rate, window length, harmonics, and thresholds once we start testing with our own hardware. The next step for next week will be converting this to C/C++ using tools like Claude so that it runs on the ESP32 as well as testing on real datasets to make sure all parts are working (this was only tested this week with synthetic data).

For now, the classifier compares the EEG against 8.57, 12, and 15 Hz references and gives each one a CCA score. The highest score is the predicted command. I also added confidence and winner-vs-runner-up margin checks so the system can eventually reject unclear inputs instead of always forcing a YES, NO, or HELP result. This is exactly what we documented for our design report and what Theodora presented last week. I have not chosen the final thresholds yet because these need to be determined from our own calibration recordings.

Here is a screenshot of the repository:

I (using Claude) also wrote automated tests for all the different coding stages. Right now, 193 tests pass with no failures. These cover the reference signals, filtering, CCA calculations, classification/rejection logic, synthetic EEG generation, metrics, and data loading.

Before moving to real EEG, I tested everything using synthetic data where I already knew the correct answer. I generated fake EEG containing 8.57, 12, or 15 Hz signals, then added noise, drift, 60 Hz interference, and differences between channels. For example, a synthetic 12 Hz trial should produce the largest CCA correlation for the 12 Hz reference rather than 8.57 or 15 Hz. There was no noise in these data points so obviously I expected a big spike and strong correlation scores. This was just to test if the processing worked. I repeated this for all three commands.

Example CCA output:

I cannot upload thet tests.csv files due to security reasons on WordPress blocking me.

For clean signals, the correct CCA reference clearly gives the highest score for all three commands as expected.

I then added much more noise and also tested pure noise, off-target signals, and ambiguous mixtures. The correct reference still tended to score highest for valid trials, but the scores became closer together as the inputs got worse. This was useful because it showed exactly why we need rejection logic instead of just picking the largest score every time.

Python is being used as our reference implementation and analysis environment, while the final filtering, CCA, and rejection logic will run in C/C++ on the ESP32-S3.

Schedule

I am on track right now. Next week is going to be busy because we also need to finish the design report and get the PCB ready to send out.

Deliverables for Next Week

Finalize and send out the PCB design (will help with layout and BOM finalization), test CCA against Wang et al. SSVEP dataset and once it works, port the Python to C/C++ for the ESP32 and finish my parts for the design report.

Atharv Kashyap‘s Status Report for 09/26/2026

I was sick this week and missed Wednesday’s class, as well as some targets our team had set between ourselves for the design proposal. This caused us to be a little rushed at the end of the week before slides and this report were due. I did not communicate this well enough to my team, so one thing I need to improve is communicating delays earlier instead of waiting until a deadline has passed.

My planned work also changed after our discussion with Prof. Byron Yu. He brought up several valid concerns regarding what were controlled and confounding variables in the experimentations we planned to build our model around. We realized that public SSVEP datasets were collected under specific experimental conditions that do not necessarily match our electrodes, hardware, display, or environment. Instead of relying on those results to validate our system, I developed an initial plan for collecting our own data as written below:

  1. Keep electrode placement, reference, viewing distance, screen brightness, lighting, sampling rate, and trial duration consistent. Here are some preliminary numbers. For our initial testing, we will use O1, Oz, O2, and POz over the visual cortex with the same reference and bias placement (earlobes) for every session. The display will be fixed at 60 Hz, approximately 60 cm from the user, with constant brightness and room lighting. EEG will be sampled at 250 Samples/sec and processed over 2–3 second windows. Each command will initially be tested over 30 randomized trials, split into blocks of 10 with short breaks to reduce fatigue. These values will remain fixed during testing so changes in classification performance can be attributed primarily to the EEG response rather than changes in the experimental setup.
  2. Use our three stimuli at 8.57, 12, and 15 Hz with the display fixed at 60 Hz. These numbers have changed since before. The reason was that studies showed SSVEP responses are strongest at the stimulus frequency and can also appear at its harmonics, so we wanted frequencies that were sufficiently separated without one being a simple harmonic of another. We also wanted frequencies that our 60 Hz display could reproduce exactly using integer frame periods. Our current set uses 7, 5, and 4 frames per cycle, giving 8.57, 12, and 15 Hz. This keeps all three targets in a commonly used SSVEP frequency range while avoiding direct harmonic overlap between our three fundamental frequencies.
  3. First test each frequency individually and verify that it appears in the measured EEG.
  4. Then collect randomized YES/NO/HELP trials in blocks with rest periods.

Finally, I completed a working stimulus renderer for YES/NO/HELP. It generates the three frame-locked frequencies, checks the display refresh rate (so it was not hardcoded to my Macbook, for example), logs the frame timing, and gives us an interface for both the presentation and later data collection.

Below is a screenshot of the interface:

AI, specifically Claude Opus, was used in its creation, as well as setting up the initial repo with README, pyproject, various pytests, and general documentation.

Schedule

I am behind schedule, in this course and my others, due to being sick and because the experimental approach changed this week. I completed my other  course’s labs early so I can dedicate more time to the project on Tuesday and Thursday’s dedicated lab time next week to catch up.

Deliverables for Next Week

I plan to implement and test the initial CCA classifier, help write the design report, and define quantitative requirements for classification/rejection and PCB testing. I will also finish documenting and testing the stimulus renderer so it is ready for our eventual EEG experiments. As a team, we plan to finish the schematic/design review, continue PCB layout and component choices, and move toward the first PCB fabrication order.

Felipe’s Status Report for 9/26/26

Progress and Accomplishments

This week I was focused on three primary things, getting initial parts ordered so we can start some testing, looking into possible headset 3D files so we can have a consistent frame for our electrodes, and looking into the DSP and software interface skeleton of the project.

For parts we wanted to get the electrodes ordered and out of the way. We ended up going with the supplier for OpenBCI which is Florida Research Instruments.

For the headset, I found the 3D File OpenBCI uses for their headset and am working to get it sized correctly. I am also working on designing a spring loaded mechanism that will ensure electrodes maintain full possible contact with the scalp.

Lastly for the DSP and software interface, I was focused on the microcontroller aspect specifically the ADC->ESP32->Computer interface. I found some solid options on how to do it, and plan to work on it further next week.

Next Week

The main goal of next week will be to finalize plans for the ADC->ESP32->Computer pipeline and start drafting an MVP we can use for testing.

Felipe’s Status Report for 9/19/2026

Tasks/Accomplishments

This week was focused on researching the workings of BCI and looking for what could be potentially suitable parts  for the project.  I mainly focused on how we could get reliable electrodes that we could use for the project while not blowing up our budget. I began by looking at parts and costs from OpenBCI. However many of the parts or kits present were too expensive. Through some further research I was able to find the company that sources some of the parts for Open BCI and they provided more affordable options.

A good part, of my focus was on understanding the different types of electrodes available. The main two being cup electrodes and dry brush electrodes. Cup electrodes are the classic type which require a conductive gel to work properly and is often used in medical applications.  Meanwhile dry brush electrodes are completely dry and have much easier setup. Technically the gold cups have a better chance for better signals but unless the dry brush completely fails we won’t use it.

The other major task this week was creating and sourcing the initial bill of materials for the analog acquisition hardware. I built a BOM with reference designator, value, manufacturer part number, unit cost, per-board quantity, total quantity, total cost, and purchasing link. I individually sourced the passive components, protection diodes, amplifiers, and trimmers rather than estimating a generic PCB cost. The current BOM contains parts such as the INA128UA instrumentation amplifier, OPA2227/OPA4227 op-amps, MMSD4448 protection diodes, precision resistors, filter capacitors, and adjustment potentiometers. For the quantities currently entered, the BOM totals approximately $228.35. This also gave us a much more concrete view of where the prototype budget is going and which components dominate cost.

More work needs to be done to see if replacements and cheaper options are available

Plans for Next Week

For next week we will be focused on drafting the first iteration of our PCBs and ordering parts, as well as trying again to contact professors with experience in the field.

On Schedule?

We are on schedule.