Josh’s Status Report (09/19)

This week, I focused mainly on researching the Intel 8088 specification and creating a block diagram for our custom CPU. I worked through how instruction fetching, decoding, operand reads, address generation, execution, and writeback connect, using an ADD instruction as a concrete example. I also studied how the bus interface unit shares memory access between instruction fetching and execution, along with how interrupts save processor state and redirect execution to a handler. While reviewing the diagram, I corrected inconsistencies in instruction decoding and address calculations and added missing data paths and control logic. This work helped me break the CPU into manageable components and better understand their interfaces before beginning RTL implementation. Next week, I plan to refine the control sequences and coordinate with Ben on the CPU bus interface so that our CPU and memory subsystem designs agree on how requests and responses are handled.