This week, my primary focus was split between final documentation for our design review presentation and advancing the 2C02 PPU hardware implementation. For the group presentation, I was responsible for drafting the implementation plan and the testing plan, specifically detailing how we will validate cycle accuracy across the CPU PPU interface.
On the technical side, I successfully finalized the Verilog implementation for the background rendering and pattern table fetching logic. This involved mapping the internal VRAM addresses to the pattern table data fetched from the emulated cartridge memory. Additionally, I began developing a dedicated testbench to verify PPU register read/write timing.
I am currently on schedule. Having finalized the background rendering logic this week, I am exactly where I planned to be in our internal timeline. For the upcoming week, I hope to complete finalizing the PPU testbench and verify that register access timing matches the original hardware specifications. In addition, I will begin the RTL implementation for sprite rendering logic, including the priority evaluation for overlapping sprites.