For this week, I mainly contributed to the proposal presentation slides and prepared for the presentation. On Monday, I presented our proposal to the class. Later this week, I researched on open source information about the implementation of some of the hardware in the NES, such as the 2A03 CPU and the 2C02 PPU. I researched more into the open source implementation of the 2C02 PPU, and worked on extracting and modifying its I/O interface. I focused on extracting the core rendering logic and modifying the top-level interface to support our specific ZYNQ-7000 FPGA pin constraints
I am currently on schedule. According to our planed timeline, I will need to finish the PPU’s pattern table. I have already obtained some data in this regard, and I will finish this in time.
For next week, I I aim to complete the following tasks. I will finalize the implementation of the background rendering and pattern table fetching logic. I will then start on generating a testbench to verify PPU register read/write timing against the 2C02 technical specifications.