This week I focused on implementing the RTL for the frequency modulation component of our digital synthesizer and began planning the ADSR envelope component.
For the FM component, I implemented a 24-bit phase accumulator to track the phase of the waveform. The circuit takes in a tuning word representing the carrier frequency, a modulation signal, and a scaling factor. It then uses them to update the phase accumulator every clock signal, outputting the modulated phase, which will then be used for wave table lookup. FM computation is coupled with the phase accumulator, so that we can ensure consistent behavior across output types.
Additionally, I began planning the ADSR envelope generator, mainly sketching out the finite state machine for the system. I also began writing Matlab scripts so that I could test simulation output of the FM component against a reference model, but had to spent most of my time brushing up on the language, since it has been about two years since I had used it.
Next week, I hope to verify the RTL for the frequency modulation component, sketch out the data path for the ADSR module, and begin implementing the RTL for it.