This week I worked on determining our solution approach for how to represent the audio we will be processing.
One option is to make no noticeable change, and just treat every number as a standard int interpretation (similar to how something like C would do it). This is beneficial because of its simplicity, and will require fewer hardware resources, since all the arithmetic is already provided with FPGA primitives.
However, this may cause problems later down the line. Since our CODEC works from an I2S protocol with 24-bit precision, and it expects amplitudes in the form of -1 to 1, we would have to do some conversion at the end. Alternatively, we can adopt a fixed-point notation to represent this amplitude range. Namely, Q 1.23 provides one sign bit and 23 fractional bits, allowing us to represent the range of -1 to 1 nicely. However, this comes at the additional cost of extra hardware to instantiate the proper arithmetic. The engineering effort is relatively low, since there are already Verilog libraries for this kind of work, but the hardware utilization will still be higher.
Ultimately, we favored the Q1.23 form. I also worked on the block diagram for the design presentation, and am excited to start working on the RTL next week!