This week didn’t bring us any new risks. In order to minimize risk we made progress on the core components of our design. I worked on writing the pipeline, tests, testing infrastructure, and sub-units. Jae even managed to finish the DSKY which was a risk of not working or being complete which is now completely mitigated because it is done.
Only minor design changes occurred in the pipeline with almost no cost because it just meant writing the SystemVerilog a bit differently than expected and changing the diagram (so minor that I didn’t think it was worth including the diagram). Also, another minor change was that the protocol to be used for FPGA-DSKY communication will be UART and not I2C. This was changed due to the ease of use of UART compared to I2C and the fact that using a bus was not needed.
On the software side, we are working on figuring out the AXI protocol for ARM-FPGA communication for the demo. Goal for next week is to install Linux on the ARM core and attempt sending and receiving of data with the FPGA.
