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Tom’s Status Report for 4/2

This week I gave up on the HDMI pipeline on the pynq zynq board. After 3 weeks of trying, I couldn’t get a successful toolchain for the board working. The Pynq (also sold as the Arty Z7 board) was discontinued, and no support exists after petalinux 2017, meaning we need to use archived tools that no longer work on modern linux versions. Additionally, the hdmi pipeline was finicky and required regenerating the bitstream and rebuilding the linux image to change resolutions. This process takes several hours, and we were unable to successfully get the pynq to recognize an hdmi display and output data.

Switching to the ultra96 board meant we could make use of the UltraScale+ Zynq’s hardware GPU and skip the complex design of an framebuffer/hdmi pipeline. Since switching, we’ve already brought up hdmi and i2c drivers on the ps system, and built bitstreams and petalinux images. I successfully wrote a driver to interface with the knobs over i2c, and have been working on deploying Qt to the ultra96 to build the gui. So far, I’ve successfully configured petalinux to include Qt binaries, but building the Qt binaries has already taken multiple hours and might be an overnight process.

This week I’m hoping to deploy the Qt gui to the ultra96 and a write user-space drivers for Graham’s AXI peripheral work.

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Graham’s Status Report for 3/26/22

This week, I finished the Front Panel design and am in contact with Ed Wojciechowski to facilitate water jet cutting. This will be simple and cheap hopefully. I sourced the MIDI input board and ethernet coupler for our rear panel. We still need audio jacks, DCin and power switch. I think we can simply find those around. We have to figure out this AXI interface and protocols soon so we can finally communicate with the FPGA modules. We should produce the MVP in the next two weeks, including bare minimum oscillators, integrated MIDI, and a few encoders.

We are definitely behind schedule. I believe we should have had the MVP ready by now based on our gantt chart. However, in hindsight, this goal was a bit ambitious. I am confident we will be viable by next weekend! In order to achieve this I will be more realistic with our goals and put maximum effort into all the elements of the MVP in the coming week.

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Sam’s Status Report for 3/19/22

Last week I wanted to finish the power supply section (only the 3.3v rails are done, need to add low noise 5V regulators too) and to get a solid plan for the front panel interface. I accomplished both of these, which technically puts me on schedule. The positive and negative 5V rails are used for the analog path (VCF and VCA both require split rails) and the 3.3V is for logic, FPGA, encoders, etc. We solidified the plan for front panel interface including number and function of rotary encoders. I ordered all the front panel stuff, including knobs, encoders, and quadrature to I2C PCBs. Each encoder will have a small PCB behind it to count the quadrature pulses and put all of them on the same I2C bus which we will be able to poll with the SoC.

Next week, I want to make significant progress in PCB layout. The schematic is becoming more firm and I can start to do actual layout soon. At a minimum, I would like to start the analog path layout next week.

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Sam’s Status Report for 2/26/22

This week, I completed the analog path schematic design which was the goal I stated last week. As a group, we decided to change the synthesizer architecture to be duophonic rather than polyphonic, so there are two VCFs and VCAs with independent control signals. I added ample power supply decoupling and RF chokes to separate the analog and digital supplies.  There is a high speed I2S DAC for audio which has two channels (right, left) followed by two VCFs with both adjustable cutoff frequency and resonance, then two VCAs. The output of the VCAs is buffered with opamps and an 8-channel I2C DAC is used to generate the control signals which drive VCFs and VCAs.

Completing this puts me perfectly on schedule, which is great. For next week, I want to finish the power supply section (only the 3.3v rails are done, need to add low noise 5V regulators too) and get a solid plan for the front panel interface. This includes ordering the correct number of potentiometers, rotary encoders, and knobs as well as starting the schematic design.

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Team Status Report for 2/26/22

At this time, we have a clear path ahead of us for creating the PROGNOSTICATOR-6. We made changes to the original design last week, but we have not altered it again. Since simplifying our design, our greatest challenges seem to be integration and implementing some complex aspects of synthesis. The analog path may be simpler now, but as Sam discussed in the design review presentation, we still must be cautious of generating noise.

It may be risky to put too much emphasis on the user interface and aesthetics when we have many other elements of the project to consider. What use is a synthesizer that looks pretty, but does not sound good! If there is an overwhelming amount of work on the FPGA, Sam and Graham will need to spend more time on that to ensure that the essentials are completed in time.

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Graham’s Status Report for 2/26/22

This week, I wrote a python keyboard program using pygame.midi.  This was easier than anticipated. However, it still exists entirely within my laptop. I attempted to add oscillators and modulators to truly make a digital synthesizer, this is a work in progress. On the ZYNQ, this program can take MIDI input from our controller along with input from encoders. From there, we may add more simple effects in software after we have worked out the complex elements of the synthesizer.

I am still slightly behind on my progress. Last week, I said I would have liked to have some software on the ZYNQ that produces a signal today. I am very confident we can achieve that this week. I am going to put in additional hours over the break to learn to work with Vivado and a Zedboard from the ECE Inventory since Tom will have the PYNQ. This week: I will work with Sam to decide a layout of encoders that makes sense for the PCB, complete the MIDI portion of the synthesizer, and continue to develop the front panel design.

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Tom’s Status Report for 2/26/22

This week was mostly research for the video pipeline, and I began working on the Qt application for the linux side of the project.

The video pipeline for the Zynq uses the AXI VDMA core to transfer data out of the framebuffer which is stored in the Zynq’s memory. (The PS and the PL share the same memory.) A video timing controller creates the pulses for vsync, hsync, etc for the HDMI phy.

Lauri's blog | Connecting test pattern generator to VGA output on ZYBO

The main application will run with Qt and draw to the framebuffer. I need to test this, but petalinux (Xilinx’s linux distribution) has finished drivers for the AXI-VDMA system, so as long as I followed the spec correctly Qt should be able to draw to the hdmi output without any real setup. This is tricky and might be very unreliable at first. The Qt application is multithreaded C++ and will do basically all of the complex work for the synthesis, including envelopes, wavetable selection/loading, video output, reading inputs from encoders, and voice allocation.

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Graham’s Status Report for 2/19/22

This week, I installed Vivado on my personal laptop and began familiarizing myself with our virtual PYNQ-Z2 board. I ran through some tutorials using Vivado’s behavioral simulation and this week, I would like to see it function correctly on our hardware. It will be very useful to have Vivado available during our biweekly class time!

As a team this week, we narrowed down a specific number and allocation of knobs and buttons for the front panel. There are a few things to still consider, but I went ahead and made a rudimentary CAD assembly for the front panel. This includes 25 knobs, an LED matrix, a screen, and three buttons for choosing patches. It is a rudimentary design, but the dimensions worked out well (2.5×8.5×37.5in) and there is room for adjustment. We will talk about it together this week and I will make the necessary adjustments.

Next week, I will have completed a midi interface in the ZYNQ and have it output a noise or at least the name of a note in text. I am a little behind schedule, but we all had some major design choices to agree on this week. Now that we have done that, I believe we can get really get to work.

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Sam’s Status Report for 2/20/22

This week I worked on schematic design and analog filter path design. Our initial project specifications and block diagrams were vague so we worked to solidify those and nail down the specific filter/analog architecture.  To save time and help increase the odds of success we traded the discrete switched-capacitor filter architecture for monolithic voltage controlled filter integrated circuits. We will have a low pass filter with programmable cutoff frequency and resonance that are adjusted proportional to a current value that comes from a control signal DAC. There is also a main (I2S) DAC for the audio path. The output of the filter is then fed into a voltage controlled amplifier before the “line out” jack.

The analog path also requires a very low noise split-rail voltage supply. I designed 2 switching regulator circuit that convert a noisy 12V input to +/- 3.3V (extremely low noise). After some research, I decided to separate analog and digital grounds with an inductive choke to connect them.

This is good progress but is about 1 week behind according to our gantt chart. To rectify this, I plan on having a final filter schematic for next week so that I can begin PCB layout ASAP. In the meantime we can also work on sourcing the parts as we will likely need to order from a few different sources.

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Team status report for 2/20/2022

We locked down our synth architecture this week, and decided to switch from a true 6-voiced polyphonic synthesizer to a paraphonic synthesizer. We determined that the io usage and complexity from 6 true analog voices was too complex and risky to implement, and after testing paraphonic synthesizers we determined that the sound was good enough. Basically, paraphonic synthesizers work by using a single global “gate” where the filter envelopes of each note are synchronized, and resets only after all notes are released. This is different than a true polyphonic instrument, but acceptable for playing chords and monophonic melodies

For hardware, this means we’re using one VCF chip, one i2s stereo DAC, and one additional DAC for controlling the parameters of the VCF chip. We may implement two voices in hardware to create a “duophonic” synthesizer, which would allow true stereo patches and a small level of polyphony.