Category: Team Status Reports

This week our team gave the final presentation. Each of our teammates is working on their part for the remainder of the project. Our final video is almost done, kudos to Michelle.

We will be completing our project this weekend and finishing the remainder of the video.

This week, each of us worked on a special effect (ADSR, unison detune, and arpeggiator). We performed some verifications of our system, and we were able to resolve any issues we encountered after communicating online. In preparation for the presentation next week, we started working on a slide deck, and we will probably be helping our presenting team member practice prior to the actual presentation.

Currently on our Github repo, the system on our main branch is several commits behind, as our effects are all pushed onto separate branches. Next week, we will be focusing on integrating and producing a complete product on the main branch. The biggest issue we may encounter is that we have slightly different configurations across our branches, but this issue shouldn’t be too much of a hassle, since we tried to write robust code.

This week our team is a little bit behind. According to the plan, we should be able to finish this week, but we are still working on the last two features, ADSR envelopes and the arpeggiator. We anticipate that we need to work on our project a lot more next week. Our to-dos include:

• finish our final presentation slides and practice it
• verification and testing
• finish and integrate all features

The biggest risk factor to our project now is time. As finals and all the end-of-semester projects kick in, we are finding it harder and harder to consistently work on our project. What we will do is to check in with each other on a more frequent basis in the following week, perhaps by setting up an additional meeting time.

This week our team has worked a lot on integrating the implemented functionalities. Jiuling worked a lot on this aspect by refactoring our repository. A significant problem that occurred this week was that the current clock rate (50MHz) is too fast for memory access needed for the sine wave oscillator. We will try to resolve this issue by using a slower clock (25MHz or 12.5 MHz).

There is a slight cost of latency to this change, but since we set a pretty loose goal for latency (10ms), we are still on a good track of hitting this metric.

In addition, all three members have started on checkpoint three tasks and our team is overall on track for this week. However, we anticipate that lots of work will need to be done in the following week as we will prepare for the interim demo and finish up on our checkpoint three tasks simultaneously.

This week, we used one week out of our planned slack time because we were experiencing hardships in the hardware interface between MIDI and the FPGA. We wanted to take time this week and try to get the hardware working before moving on to our next checkpoint. The main reason for this difficulty is the fact that the cable that we bought for connecting the MIDI to the MIDI breakout board isn’t functional. So, instead of processing our MIDI input with MIDI –> breakout board –> FPGA, we decided to go directly from MIDI to FPGA with a USB connection. Fortunately, we were able to get MIDI signal transmission working via USB, and we are actually able to hear audible output from a DAC.

We have updated our Gantt chart to reflect this change in schedule.

• This week, we have decided on the interface between the components and stages of the system.
• The most significant risk is that we have not been able to get meaningful signals from the MIDI breakout board. We are considering using USB-B to USB-A connection between the keyboard and FPGA instead.

• This week, we discussed Prof. Sullivan’s feedback received from the design review presentation and decided to leave the filter as an add-on feature to the end if we have time given this semester is shorter.
• The most significant risk so far was setting up the synthesis and simulation environment as this is new to all of us and involves installing a Windows system on Mac for two members. Luckily, we have had the setups mostly working and the experience is transferrable, so hopefully by the end of next week all of us can work smoothly.
• We started writing the design review report.
• We have set up a project structure that minimizes merge conflict.

This week, we worked collectively on finalizing our system design. By compiling the block diagram, we are able to think more fundamentally about our approach to the technical challenges. For instance, we made the design decision that the phase-shifting harmonizer will be implemented with adding feed-back loops to the oscillators, instead of modifying the mixer module. With a furthered understanding of our project, we made the slides for our design review presentation next week, while also keeping in mind the feedback that we received for our proposal presentation.

The most significant risks and contingency plans are:

• Unfamiliarity with the SystemVerilog environment and long ramp-up time — get our hands onto the FPGAs as soon as possible and set up the simulation environment together
• Insufficient time estimated for each task — allotted slack time of 14 days
• Integration and synthesis could require lots of coordination and time — made integration and synthesis periods into their own tasks so that we account for these events too

As of now, we are just starting to follow our Gantt chart and have not made any changes to the existing system or the schedule.

We have not encountered any risks so far into our design process, as we are still in the preliminary planning stage. However, as we are filling out our Gantt chart, we realized that we have very limited time, much less than we initially expected. As for now, we are keeping two weeks of slack time at the end of our implementation.