Category: Hongrun’s Status Reports

This week I have mostly wrapped up my part of the project this week by implementing the bonus wavetable oscillator features:

1. I wrote a script that converts the .raw files that Michelle generated from an open-source library to .vm formats. I used a module for taking in the .raw files as a stream of 16-bit data samples and then converted each data sample into 24-bit and storing each of them in order in a .vm file because the AUDIO_BIT_WIDTH we set for our project was 24.
2. I changed the configuration variables in SystemVerilog so that now it would give our oscillators access to the new wavetables in addition to sqr/sin/tri. This was not that difficult because I was able to reuse a lot of the code in the sqr/sin/tri wavetable oscillator module. Our previous features such as ADSR and PWM will still work on the new wavetables.
3. I modified the ChipInterface module to allow our users to choose waveforms from the switches on the FPGA. We would have loved to move this interface onto our keyboard, but we, unfortunately, ran out of knobs to do so.

What is left for next week is very minimal, just mostly merging my code with Jolin’s ongoing progress with the Record and Cycle functionality. I will also help with Michelle’s work on the video and our report together!

This week I got a lot done and am wrapping up my personal tasks for this project in general. I did the following:

1. Finish ADSR implementation and successfully synthesized it.
2. After Michelle did frequency testing and found out that our system has very severe pitch deviation, I changed two things to improve the problem to a degree that is acceptable: a). increasing audio frequency rate (50kHz -> 400kHz) before downgrading to the industry standard of 44.1kHz, b). increasing sample width from 16 to 19. Since our code has very good use of macro-parameters thanks to Jolin’s integration efforts, these steps were done without too much difficulty. Right now, we are meeting our frequency requirements for all the notes below C6. This is not ideal, but within expectation, because the nature of using a division lookup table suffers the loss of accuracy in higher octaves.
3. I went to the capstone lab to gather testing metrics on latency and frequency distortion using the oscilloscope and organized them into data that we will present in the final presentation. I also took lots of screenshots and some videos on some of our features, e.g. ADSR, PWM, and polyphony. These can be used in our final videos.

I am currently on track and looking to finish my work on time.

Before the final presentation, I need to:

1. Write a Python script to compare the shape of our three fundamental waveforms with the ideal shape in order to evaluate our waveform generation approach using a period table and a division table
2. Help make the testing and verification part of the final presentation slides and do a mock session to help Jolin prepare for the real presentation

Lastly, after the final presentation but before the demo, I am planning to do one last adjustment to my part of the project by tweaking the ADSR module to prolong the maximum duration of each stage. I planned the stages to be 1 second, but with the unforeseen upgrade of frequency rate, this number dropped down to 1/8th of a second… I need to increase the bandwidth of my envelopes to counteract this side-effect.

This week I focused on two items:

• Finish simulation testing on ADSR envelopes: I ran a simulation using vcs to validate that my code for the ADSR functionality is working.
• Planned verification and testing for the entire system: I reviewed our design material to look for parameters that I need to test for in the verification and testing phase. This included correctness metrics, such as whether the waveforms we produced are the same as that we have obtained using matlab scripts; how much do the pitches produced by our synthesizer vary from the 12-equal temperament standard; how much delay there is from the time the FPGA gets a signal to the time that a signal is played via the DAC as an output…

I am a little behind this week, since the original plan was to get the ADSR synthesized, but I only managed to get the simulation working.

Next week I will,

• Synthesize the ADSR module to get and integrate it with the rest of the system
• Carry out the verification and testing on campus using oscilloscopes. This might take a little effort because I am not so familiar with the trigger function, but I will try my best to get the numbers for my teams so that we could present these on the week of 5/3.

This week I focused on developing the ADSR module due for our third checkpoint. I looked into the triangle wave oscillator code because conceptually the A, D, and R stages should be implemented in a similar fashion to the triangle wave oscillator. After I am done with the development I will move onto writing a testbench and use the generated waveform for affirming the correctness of the program.

As far as progress goes, I am on track.

Next week, I will focus on the following:

1. Continue developing the ADSR module
2. Get the project to synthesize on a lower clock rate (See more about this in the team status report)

This week I did the following:

1. Got the MIDI interface circuit to work with a new TRS cable
2. Got the DAC circuit to work

Since these are the goals for this week, I met my goals.

I am basically on track after taking a week of slack time to make up. I am happy to get the physical interfaces working and at least get some sounds through our system.

For next week, I will focus on developing the ADSR envelope module.

For the past two weeks I worked on:

1. Building the MIDI interface circuit. This did not turn out well — as I probed the circuit with an oscilloscope and tested an Arduino script (See Step 10 in the link) to see if it was working. The waveform I got from the scope was very noisy; the Arduino script did not yield any sound to be played as it should. I arrived at the hypothesis that the midi breakout board was broken either on arrival or due to soldering. I ordered another one and tested it — unfortunately, I got the same result. I am having a debug session with my teammates today to see if I can get any progress. If not, we will ask for help from other people.
2. I wrote the script for the MIDI deserializer+decoder and simulated it successfully.
3. I wrote the script for interfacing with the audio CODEC on the FPGA. I studied the I2C protocol and the audio CODEC specification. I then found a script online that does a similar job (except it reads data from memory) — I was able to synthesize it and get it to play music from memory on my board. I am still in the progress of integrating this code with Michelle’s sine oscillator.
4. I wrote the script for the mixer and simulated it.

My progress for this week was mainly blocked by the issues with the physical MIDI interface. I was, therefore, unable to finish 1/3 of my tasks for this week. In order to unblock Jiuling from her checkpoint 2 tasks, I found her a Python script that takes in USB MIDI signals and prints out the MIDI bytes.

My tasks for the next week include:

1. Developing the ADSR module
2. Finish ckpt1 integration and get some sounds to play out from the audio CODEC

This week, I did 90% of what I have planned:

1. I tried to set up a Linux subsystem on my Windows partition to do simulation locally, but that did not quite work out because I could not figure out how to share my files in the Windows system with the Linux subsystem
2. I resorted to using the ECE virtual machine as my development and simulation environment (with VCS). I hope that although all of us will probably be using different environments (Jiuling will be using ModelSim while Michelle is still deciding), our integration stages will still work out.
3. As a team, we figured out our GitHub project structure and workflow
4. I soldered my MIDI breakout board
5. Started my part of the design report, progress is at 50%

I will catch up on No.5 shortly — hopefully, finish my part this evening.

Next week is a heavily loaded week, but I plan to:

1. Finish the design report with my teammates
2. Understand and write up a summary of MIDI specifications to share with my teammates
3. Finish the MIDI keyboard to FPGA circuit
4. Draw datapath and FSM for decoding MIDI messages and have my teammates critique them
5. Finish simulation of the MIDI decoder

This week I completed:

1. Ordering and receiving all lab materials
2. Setting up a windows partition on my laptop
3. Setting up the synthesis environment on my windows partition
4. Finishing a Matlab testing script on the frequency modulation feature
5. Design slides for presentation next week

As a group, we made pretty substantial changes to our Gantt chart this week per the suggestions we got from the proposal presentation as well as Prof. Sullivan. With the new timeline, I am currently on track.

Next week I will focus on

1. setting up a Linux subsystem
2. configuring the simulation environment of our project
3. figuring out the GitHub repo file structure and our GitHub workflow with my teammates
4. soldering our MIDI breakout board
5. writing the design report with my teammates

This week, I have achieved a couple of things:

1. done extensive reading around our project which provided me lots of insights into feature selection, material selection, and best practices. I have compiled a spreadsheet of all the information in a spreadsheet and shared it with my teammates so that they would have access as well: https://docs.google.com/spreadsheets/d/1upJKRxLvryDJerdH9ke7Zp3LpNwuv9ba_4qSlSnNCI8/edit?usp=sharing.
2. my teammate and I collaboratively completed the proposal presentation slides
3. practice my upcoming 12-minute proposal presentation

My progress is on track as well as that of my teams’ as of now.

Next week, my tasks include:

1. giving a presentation
2. compiling a bill of materials with my teammates
3. work with the course staff on ordering them.