The most significant risks and contingency plans are:
- Unfamiliarity with the SystemVerilog environment and long ramp-up time — get our hands onto the FPGAs as soon as possible and set up the simulation environment together
- Insufficient time estimated for each task — allotted slack time of 14 days
- Integration and synthesis could require lots of coordination and time — made integration and synthesis periods into their own tasks so that we account for these events too
As of now, we are just starting to follow our Gantt chart and have not made any changes to the existing system or the schedule.