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Xingran’s Status Report for 3/6/2021

This week I have finalized the microcontroller block diagram, though we had several component/interfaces changes this week and there were several intermediate versions. The microcontroller design document is also updated accordingly.

Microcontroller Program Design_0306

I have setup the STM32CubeIDE environment for developing the stm32f4 board, and looked at the examples and tools for setting up pins, controlling interrupts, etc..

I had made some feasibility studies including:

  1.  Multiplexing 4 audio inputs at the same time. I made sure the ADC we use have TDM output capabilities, and though our board itself does not have software support for TDM protocol, with SPI interface we could read the data line in order, and get the 4 channels in order.
  2. Using DMA for frequent and high bandwidth data transfers. I confirmed that DMA can support audio input through SPI, output through I2S, and LCD output through SPI.
  3. Only using SRAM for DSP runtime data. I studied the flash on stm32 board and know that the endurance and latency of flash writes make it infeasible. So our run-time writable memory is confirmed to be only SRAM. (Sam will also mention this)

I did not finish defining all the interfaces and headers in program, because we had several component and interface changes which lead to overall software design change. There will hopefully be no more changes in the future and I will finish the following next week:

define code interfaces/function prototypes; test some of the protocols on the discovery board (I2C, SPI, UART).

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Adam’s Status Report for 3/6/2021

REV 1 SCHEMATICS: I completed the schematics for Rev 1 and sent them out for review on Monday (3/1/2021). The response from our reviewers (our TA and advisor) was mostly positive, but our TA identified a new ADC component which could offer superior performance over our existing solution, which led me to redesign the input stage with input from my teammates and our advisor on Thursday/Friday. The new input stage features a 4-channel audio ADC which communicates with the microprocessor on SPI and a new audio-class amplifier for the preamp block.

REV 1 LAYOUT: In parallel with the above, I began laying out the Rev 1 PCB board. Rev 1 is a mixed signal board including both audio and RF signal paths, as well as moderate-frequency digital signals, necessitating care in layout.

As can be seen in the image above, I’ve finished internal layout for most of the main blocks, including the Analog Effect, LCD bus, and BM83. Most of the Power Module and part of the UI module remains to be routed, but I expect that I am close to completion because the routing for these remaining components is less complex than what I have done so far.

DESIGN REVIEW PRESENTATION: I will be delivering the design presentation next week, so I have been working together with my teammates to create the slides and understand the content I need to present, which includes substantial work that was not done by me. We plan to hold a dry run presentation on Sunday before the slides are due.

I had previously hoped to finish the layout and order the board by the end of this weekend. However, due to the late redesign with the ADC, it seems more realistic to let this deadline slip by a few days and order the PCB before Wednesday. Finishing the layout and all of the associated tasks necessary to order this PCB will be the main focus of my effort in this coming week, along with participating in the design review process. Overall impact of this change on our project schedule should be minimal.