Team C2: WiFi Localization

This week we spent a lot of time on the design aspect of the project in order to put out the presentation and report.

I focused mainly on the FPGA and onward part of the block diagram which ended up being not complete upon uploading the diagram to our presentation which was our fault. However, I worked on understanding how the signals should be coming into the FPGA and formatted so I could start writing block diagrams for the internal SystemVerilog modules. Upon figuring out format of the signals I roughly figured out that the 32 input signals must then be time delayed internally in order to create a proper signal that the DSP Beamforming algorithm module would take as an input. Once the signals have been time delayed the DSP algorithm as shown in our block diagram would run the proper computations to output one signal. This signal will then be run through another module that would take the amplitude of this signal in order to get a “pixel” intensity value for the heatmap. The pixel in this case is actually a grid box as shown in the Artist’s Rendition. This value will then sent to our code which will render the heatmap overlaying the input video feed which will be sent out via mini DisplayPort to a monitor.

This week and in the upcoming one I will be working on creating a detailed block diagram and specification for the FPGA SV modules and heatmap creation for the design report. I will continue to work on refining the design and starting to write code/pseudo-code which is on schedule for writing and then hopefully testing.

This week has been very conceptual in the next steps of our project. Since I am primarily focused with the hardware and the latter steps of our project there isn’t too much I have been able to physically do before having a testing implementation of the antenna PCB to start designing the SystemVerilog modules.

Since last week I have narrowed our FPGA down to using the Zynq96 Ultra v2 Board since this board has an MPSoc which is allows for more parallelism and better efficiency than the SoC FPGA’s in Capstone stock. This board has enough GPIO’s and the current stock SoC FPGA’s do not have enough GPIO pins for our proposed design. Although the traditional FPGA’s may have enough GPIO they do not have the flexibility of using High Level Synthesis (HLS) which allows us to write in C which will synthesize to SystemVerilog (SV) which will increase workflow efficiency since in some cases it is much easier to implement algorithms in C rather than SV. I have experience with this board more than any other board listed as well which will allow for a better turnover rate for implementation since we will spend much less time trying to set up and learn the board.

Furthermore since last week I have thought about a more specific testing metric and we decided one a % accuracy of relative areas rather than the number of devices. This is because if two devices are stacked on each other we will not see readily see 2 devices on the heatmap but rather that the location has a strong WiFi signal and so we would like to accurately locate device locations rather than the number of devices.

In the upcoming week I will  start looking into the HDL side of things and trying to find DSP modules and algorithms that we may be able to use depending on the kind of input data we will get, format, etc.

This week I spent a long time trying to narrow the scope of our project and critiquing the different parts of our approach. We had a very broad sense of the purpose our project with no definitive and interesting use cases which led to making a weak argument for our project. From this I was able to come up with very specific use cases that would be used in the realm of security and police enforcement since this was one of the important parts for pitching our idea.

Together, we were able to decide that we would localize WiFi devices in a standard bedroom sized area. I deduced that 1Hz response would be a reasonable target metric for real-time detection so I looked into FPGA’s that could support the signal processing. Some FPGA’s that could be used are the Zynq Ultra96 v2 and Terasic DE10-Nano since they are relatively cheap, easy to work with, and I have experience using the two devices. Their form factor is quite small and light and so it fits with our design in terms of size and mobility since it isn’t too heavy.

Lastly I spent time trying to narrow our testing methods so that they were specific metrics that would address some of our technical challenges and goals mentioned during the presentation. One thing that we will need to work on, however, is determining a specific number of devices to locate since we were very general with our proposal and only determined lobe-width.

In addition to determining how many devices to locate, I will start working on looking to signal processing modules that we can use in conjunction with the algorithms we will be using. Finding IP’s will make the programming part much easier and will allow us to interface with the embedded parts smoother so that we don’t have to write our own algorithms/interfaces.