This week has been very conceptual in the next steps of our project. Since I am primarily focused with the hardware and the latter steps of our project there isn’t too much I have been able to physically do before having a testing implementation of the antenna PCB to start designing the SystemVerilog modules.
Since last week I have narrowed our FPGA down to using the Zynq96 Ultra v2 Board since this board has an MPSoc which is allows for more parallelism and better efficiency than the SoC FPGA’s in Capstone stock. This board has enough GPIO’s and the current stock SoC FPGA’s do not have enough GPIO pins for our proposed design. Although the traditional FPGA’s may have enough GPIO they do not have the flexibility of using High Level Synthesis (HLS) which allows us to write in C which will synthesize to SystemVerilog (SV) which will increase workflow efficiency since in some cases it is much easier to implement algorithms in C rather than SV. I have experience with this board more than any other board listed as well which will allow for a better turnover rate for implementation since we will spend much less time trying to set up and learn the board.
Furthermore since last week I have thought about a more specific testing metric and we decided one a % accuracy of relative areas rather than the number of devices. This is because if two devices are stacked on each other we will not see readily see 2 devices on the heatmap but rather that the location has a strong WiFi signal and so we would like to accurately locate device locations rather than the number of devices.
In the upcoming week I will start looking into the HDL side of things and trying to find DSP modules and algorithms that we may be able to use depending on the kind of input data we will get, format, etc.