This week we spent a lot of time on the design aspect of the project in order to put out the presentation and report.
I focused mainly on the FPGA and onward part of the block diagram which ended up being not complete upon uploading the diagram to our presentation which was our fault. However, I worked on understanding how the signals should be coming into the FPGA and formatted so I could start writing block diagrams for the internal SystemVerilog modules. Upon figuring out format of the signals I roughly figured out that the 32 input signals must then be time delayed internally in order to create a proper signal that the DSP Beamforming algorithm module would take as an input. Once the signals have been time delayed the DSP algorithm as shown in our block diagram would run the proper computations to output one signal. This signal will then be run through another module that would take the amplitude of this signal in order to get a “pixel” intensity value for the heatmap. The pixel in this case is actually a grid box as shown in the Artist’s Rendition. This value will then sent to our code which will render the heatmap overlaying the input video feed which will be sent out via mini DisplayPort to a monitor.
This week and in the upcoming one I will be working on creating a detailed block diagram and specification for the FPGA SV modules and heatmap creation for the design report. I will continue to work on refining the design and starting to write code/pseudo-code which is on schedule for writing and then hopefully testing.