This week’s tasks included APU implementation, PPU bug-fixing, and redesign of the PPU-CPU communication.
For context on the PPU-CPU communication redesign, a team design-review meeting was held last Saturday, which resulted in a redesign to the PPU-CPU communication. During the design phase, Joseph and Andrew had differing ideas on how the PPU-CPU communication and eventual PPU driver should work. Joseph wrote his design in the design review report: The CPU sends video data to the PPU over the AXI BUS accessible via MMIO, following strict timings. However, last weekend the team decided to switch to Andrew’s design: The CPU sends an address to the PPU, which the PPU then uses to DMA-copy video data stored in SDRAM. The main benefits of this include less coupled timings between the CPU and PPU, as well as more intuitive PPU software (with a lot of reusable code from the APU kernel module). Joseph will be implementing this next week, so some scheduling changes needed to be made.
Here are the scheduling changes and brief reasons for their occurrence:
- Moved task the “Row Buffers, VRAMs, CPU->VRAM Interface”. Joseph needed to modify the designs of the CPU-Facing VRAM Interface to be more compatible with the SDRAM. This task is mostly done, but needs to be verified along with the SDRAM DMA next week.
- Added a new task for implementing PPU-SDRAM DMA. The goal is to accomplish this next week.
- Joseph used 1 Slack Time for the Tile-Engine Implementation. Tile-Engine was difficult, and required setup and debug of a few other interdependent systems.
- Created a new APU bug task. Andrew will be working on this next week.
- Slack time for CPU used in advance for Implement Full Test Game. Required due to push back on APU timeline.
- Sprite Engine also pushed back to week of 4/19.