This week we worked on designing the datapath for the CPU. We currently have a two stage pipeline with fetch/decode/execute as stage one, and memory as the second stage. We went through each instruction and used a couple of references such as Gekkio’s Game Boy manual and the original Game Boy handbook to figure out the datapath.
I then worked on the datapath for the CPU. It was hard to get started because I am not as familiar with system Verilog, considering I haven’t taken 18-447 (currently registered for the same) and/or 18-341, but I’m hoping to learn more through capstone, and my teammates. The biggest challenge was figuring out the overall structure of the modules for the CPU, and how to represent pipelining via Verilog code.
I have started looking into memory mapping for the FPGA, and hope to have more details fleshed out for switching game state in time for the design review.
Action items for next report:
- Memory mapping for FPGA
- Controller and flash drivers