This week, I spent most of my time understanding the different types of memory on the board, writing the design document, as well as helping with the CPU FSMs. While working on the document, I realized I needed to read more into the SoC and how it integrates with the FPGA and controllers.
I worked on the introduction, memory management, qualitative requirements and SoC sub-system parts of the document.
Since the bios on the SoC has a way of interacting with the USB port (to say, decode NES Controller signals), the next question is figuring out how to get the SoC to talk to the FPGA. We plan on using the SDRAM on the FPGA, using it as MMIO accessible by SOC else, we are going to resort to the FPGA using DDR3 memory on the SOC. I am also looking into the HPS-> FPGA bridge tonight, and will have a more conclusive approach.
Here are the two manuals I am cross referencing at the moment:
Hard Processor System Technical Reference Manual
DE10 Standard User Manual
Meanwhile, SOC has access to the flash memory, can load and store game state.When a game switch happens, the SoC will let the current screen finish rendering and then stop the CPU’s execution. Once the execution is stopped, all of the CPU’s state and the memory will be saved for later re-execution, in flash memory. Afterwards, all of the state will be cleared and the new game state will be loaded in from flash to SDRAM.
By the end of Spring Break, I hope to have:
- A way of manipulating memory through SoC and FPGA
- Help with implementing CPU