Jared’s Status Report for April 4

Placing the program on the FPGA isn’t as easy as I thought it would be.

Things that were easy:

  • Following the user manual and learning pin assignments
  • writing a compliant SPI module

Things that are hard:

  • Deciphering the signals from the RPi
  • Receiving the signals correctly

Here is my current configuration for the physical board:

Followed by a screenshot in Quartus of the interface (while debugging):

The SPI module likes to act strange: Once in a while it will count too many clock cycles and receive or return a bad buffer. This doesn’t appear when connecting MISO and MOSI together (loopback), so it must be with the Pi.

I have contacted sources outside the group for help, as without an oscilloscope I don’t think I can properly assess my issue.

Next week will be dedicated to getting SPI working.

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