It’s the week of spring break, so this is a bit more concise.
We’re not going through with DE10-Nano SoC, so I’ll have to finish the SPI code soon.
A procedure for initializing the Pi 2B is finally realizable after finding one quirk: I’ve assumed this Pi had WiFi this whole time, explaining why I failed every time I’ve tried to debug it over WiFi. Because of this, progress was finally made in proper FPGA/SPI testing. Ethernet/SPI conversion is up next.
Our team has been a bit scrambled in terms of timeline, but now I realize I should finish this up as soon as possible. There are a few parts to the tasks ahead:
1. FPGA SPI protocol with cross clock-domain queueing
The only concern here are the size of the buffers required, but I’ll ask the team about that.
2. Ethernet-SPI packet conversion
This is purely converting the data to a packet and sending it to the host, and vice-versa. More buffering involved.
Once these are done I’ll have to help with more FPGA-focused tasks.