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Jeffrey’s Status Report for 10/11/2026

Status Report for Oct 4-11

Accomplishments:

One of the major tasks I worked on this week was to reevaluate our team’s decision to use an FPGA, based on feedback from the design review presentation as well as additional research. To get more information, I ran a C testbench on the Linux core of the Ultra96, simulating the workload using mock data. The results showed that the Ultra96 was able to produce a low enough latency to where we don’t need to utilize an FPGA. To further solidify the decision, I also created a testbench and ran it on the Raspberry Pico, which was also able to perform our workload with a low enough latency. The results from the testbench and the prototype device are pictured. 

Additionally, some parts for the wearable prototype arrived, so I was able to work with Matthew to start assembling the wearable prototype. We have successfully connected the Pico with the power shim and the battery, so we are just waiting on some other components like the transceiver to arrive.

Additional work went into writing the design review document, which included doing further research to expand on our requirements and solution approach as well as the writing involved to document our project. Specifically, that included researching some of the last few small parts/connectors involved on our system to have a complete bill of materials. 

My progress is on schedule. Next week I hope to get the prototype wearable completely assembled, and possibly begin writing the firmware for it.

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Jeffrey’s Status Report for 10/3/2026

This week I made progress in various areas. Earlier in the week (mainly Sunday) I worked on polishing my presentation for the design review, including adding visuals to the slides, reducing/simplifying the text on the slides,  and practicing the presentation multiple times. I also made progress towards the development of the wearable prototype, which was one of my focuses this week. I finalized the decision of the charging shim to connect to the prototype board, and I received the Pico from Matthew that will power the prototype. I also finalized some other small components need for power conversion between the FPGA and ANT array. Some other components for the prototype including the wireless transceiver and the IMU have not yet arrived, so I was limited in making further progress. However, I believe those parts have been finalized/ordered by other members and should be in soon. Additionally, I received the power adapter for the FPGA, so I was able to power the FPGA and enable the Linux core to communicate with my laptop, which took some troubleshooting. But I now have the ability to communicate and send files to the Linux core via SSH. Lastly, based off of feedback from the design presentation on Wednesday, I decided to investigate more on the design decision to use an FPGA versus traditional computer. Conceptual research has given me mixed results, so I plan on benchmarking to get concrete numbers about the latency of each. I will write a C benchmark that will perform the tasks required of the FPGA, and run it on the FPGA’s ARM core. I will then compare the latency to that I get using simulated data on SystemVerilog code running on the FPGA. I am currently in the process of writing/debugging the C test suite for the ARM Core. This task has taken precedence, since I want to make a final decision for the design document.

 

 

In terms of timeline, I completed my task of 100% finalizing the prototype parts I’m responsible for. They will be ordered either Sunday or Saturday, pending some coordination for the DigiKey order. I was not able to test the FPGA-Pico connection, since the transceiver has not arrived yet. I hope to be able to do that next week. Next week I also hope to connect the modules of the prototype if the parts arrive, and finish my benchmarking of the C code versus SystemVerilog on the FPGA’s core and fabric.