This week Ali and I focused on researching and testing different communication methods on the FPGA. We are already familiar with JTAG protocol methods, so we decided to focus on USB and Ethernet. I found that there are a bunch of demos already made specifically for the DE2-115 FPGA board that we will be using that implement different features of the board. One such test utilizes USB while another uses Ethernet. We were not able to actually run these demos together this week since we were waiting for the right cables to be ordered by the department. The demos are in chapter 6 in the manual (https://www.intel.com/content/dam/www/programmable/us/en/portal/dsn/42/doc-us-dsnbk-42-1404062209-de2-115-user-manual.pdf).
We also investigated how to use the triple speed Ethernet on the DE2-115 boards. I found that we will need to instantiate the NIOS II (a softcore microprocessor) on the board (using LUTs), which will connect to the 88E1111 Marvell PHY Chip on the board. I started looking through the documentation and short usage video chips on the NIOS II processor using their developer support tools (https://www.intel.com/content/www/us/en/programmable/documentation/lro1419794938488.html#mwh1416946569962). Unless we are willing to buy the license for the others, we will need to use the lowest performance NIOS II processor (version NIOS II/e).
I also worked a lot on the design slides for the next week’s presentations and did some practice runs as I will be the presenter for our group.
Additionally, our entire group worked together to determine which speeds we will need to meet for our project to meet its performance requirements. We ran some simulation tests and determined that we will need to use gigabit ethernet to achieve the necessary speeds.
Next week, Ali and I plan to run some of the demos and look through the code in the demos to see how they configure the NIOS II processor.