For our project, the most important design requirement is the runtime for completing tests. This runtime will consist of three components: the time it takes to send test cases to the FPGA, to actually process the tests through the DUT, and to send results back from the FPGA. Given that the FPGA runs on a fast hardware clock, we don’t expect the second component to take long. Instead, our bottleneck (and our biggest risk) will be in the communication latency to and from the FPGA.
For the next few weeks, we plan to focus our efforts on managing this risk. We will research different communication protocols available to us, pick some to implement, then pick one that meets our requirements through benchmarking.