I didn’t get as much done this week due to an onsite interview taking a large chunk of the week. However I continued testing the panning module and starting setting up a more concrete testbench that we can extend for the more complicated blocks. Essentially it consists of comparing python wav dumps with the equivalent SV wav dumps. Additionally I started implementing the verilog for the bit crushing module which zeros out the 8 LSBs.
For more of top level perspective I also been on the side stripping away the SDRAM IP block down to a simpler level just so its easier to integrate. Additionally I continued to help the team to make concrete protocols between each of these blocks for integration.