students in 760 do a variety of software projects as part of their course work. We archive links to these here.

Fall '00 Projects
In the Fall00 offering of 760, we did a timing-driven placer that placed gates under timing and chip-capacity constraint, using a mix of min-cut and iterative improvement ideas:

 

Fall '99 Projects
In the Fall99 offering of 760, we did a timing-driven floorplanner that packed rectangular objects of malleable shape under timing and geometric constraints. We got a variety of very interesting floorplanners, with many different engineering tradeoffs:

  • List goes here...coming soon...

Spring '99 Projects
In the Fall97 offering of 760, we did a timing-driven coarse placement tool using simulated annealing. The chip surface was divided into a coarse grid, and each grid cell had a capacity to hold gates. The placer had a set of critical paths to optimize (under an Elmore-based delay metric), had to minimize global wire length, and make sure not violate cell capacity bounds. In Spring99 we did the companion global router tool.

The global router again used the coarse grid partition from the placer, and was required to minimize overall wirelength. But, cells again had capacity limits--now for wiring congestion--and the goal was to violate as few capacity bounds as possible. Clearly, wirelength and congestion minimization are at odds here, which makes this an interesting project. The algorithm of choice was maze routing, although to get good results, attention to wire ordering, congestion modeling, and especially iterative ripup/reroute strategies was essential.

We got lots of great routers this semester. Here is a sampling of some of these interesting results: