18-747 Advanced Techniques in Microprocessors
Fall 2005

18-747 Paper Review Format

• Read the "Task of the Refree" by Alan Jay Smith posted on the Links page.
• Write a paragraph for each of the following:
  1. the context of the proposed research or design, the problem tackled (what was missing from prior work), and the proposed solution.
  2. list the key advantages of the proposed solution.
  3. list the key disadvantages.
  4. are there flaws in the methodology?

18-747 In-class Presentation Format

• Read Mark Hill's notes on "How to give a bad talk", posted on the Links page.

Chip Multiprocessors
Title	(1) Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing (abstract)
Read by	Aug. 31
Title	(2) Niagara: A 32-way Multithreaded SPARC Processor (abstract)
Read by	Aug. 31
Title	(3) Montecito: A Dual-Core, Dual-Thread Itanium Processor (abstract)
Read by	Sep. 7
Title	(4) Power4 System Microarchitecture (abstract)
Read by	Sep. 7
Title	(5) Power5 Tops on Bandwidth (abstract)
Read by	Sep. 12
Title	(6) Cell Moves Into the Limelight (abstract)
Read by	Sep. 12
Transactional Architecture
Title	(1) Transactional Memory: Architectural Support for Lock-Free Data Structures (abstract)
Read by	Sep. 14
Title	(2) Transactional Lock-Free Execution of Lock-Based Programs (abstract)
Read by	Sep. 14
Title	(3) Composable Memory Transactions (abstract)
Read by	Sep. 19
Title	(4) Transactional Memory Coherence and Consistency (abstract)
Read by	Sep. 19
Title	(5) Unbounded Transactional Memory (abstract)
Read by	Sep. 21
Title	(6) Virtualizing Transactional Memory (abstract)
Read by	Sep. 21
Title	(7) A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay (abstract)
Read by	Sep. 26
Title	(8) Memory State Compressors for Giga-Scale Checkpoint/Restore (abstract)
Read by	Sep. 26
Non-thread-level Parallel Machines
Title	(1) Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams (abstract)
Read by	Sep. 28
Title	(2) PipeRench: a co/processor for streaming multimedia acceleration (abstract)
Read by	Sep. 28
Title	(3) Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture (abstract)
Read by	Oct. 3
Title	(4) The Vector-Thread Architecture (abstract)
Read by	Oct. 3
Title	(5) Imagine: Media Processing with Streams (abstract)
Read by	Oct. 5
Title	(6) Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor (abstract)
Read by	Oct. 5
Title	(7) WaveScalar (abstract)
Read by	Oct. 10
Title	(8) Decoupled Software Pipelining with the Synchronization Array (abstract)
Read by	Oct. 10
Title	(9) The Energy Efficiency of IRAM Architectures (abstract)
Read by	Oct. 12
Title	(10) Smart Memories: a modular reconfigurable architecture (abstract)
Read by	Oct. 12
Memory Systems
Title	(1) Impulse: Building a Smarter Memory Controller (abstract)
Read by	Oct. 17
Title	(2) An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches (abstract)
Read by	Oct. 17
Title	(3) Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures (abstract)
Read by	Oct. 19
Title	(4) TLC: Transmission Line Caches (abstract)
Read by	Oct. 19
Title	(5) Data Cache Prefetching Using a Global History Buffer (abstract)
Read by	Oct. 24
Title	(6) Temporal Streaming of Shared Memory (abstract)
Read by	Oct. 24
Title	(7) Accurate and Complexity-Effective Spatial Pattern Prediction (abstract)
Read by	Oct. 26
Title	(8) Quantifying Load Stream Behavior (abstract)
Read by	Oct. 26
Title	(9) Microarchitecture Optimizations for Exploiting Memory-Level Parallelism (abstract)
Read by	Oct. 31
Title	(10) Continual flow pipelines (abstract)
Read by	Oct. 31
Simulation and Evaluation
Title	(1) Automatically Characterizing Large Scale Program Behavior (abstract)
Read by	Nov. 7
Title	(2) SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling (abstract)
Read by	Nov. 7
Title	(3) The Design of RPM: An FPGA-based Multiprocessor Emulator (abstract)
Read by	Nov. 9
Title	(4) A First-Order Superscalar Processor Model (abstract)
Read by	Nov. 9
Reliability-Aware Architectures
Title	(1) DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design (abstract)
Read by	Nov. 14
Title	(2) Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures (abstract)
Read by	Nov. 14
Title	(3) A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor (abstract)
Read by	Nov. 16
Title	(4) NonStop Advanced Architecture (abstract)
Read by	Nov. 16
Title	(5) ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors (abstract)
Read by	Nov. 21
Title	(6) SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery (abstract)
Read by	Nov. 21
Title	(7) The Case for Lifetime Reliability-Aware Microprocessors (abstract)
Read by	Nov. 28
Title	(8) TRUSS IEEE Micro special issue (abstract)
Read by	Nov. 28
Variability-Tolerant Architectures
Title	(1) Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation (abstract)
Read by	Nov. 30
Title	(2) Temperature-Aware Microarchitecture (abstract)
Read by	Nov. 30
Title	(3) Rescue: A Microarchitecture for Testability and Defect Tolerance (abstract)
Read by	Dec. 5
Title	(4) Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage (abstract)
Read by	Dec. 5

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