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Literature Review
The literature survey instructions are here: pdf
Groups
Name | Project Interests | |
---|---|---|
(Example) John Doe | john_doe@andrew.cmu.edu | Topics A and B. |
Jamie-Ben: DRAM Retention Time Profiling
Donghyuk: Direct Memory Access using Dual-Port DRAM
Samihan: Coordinated Caching and Prefetching
Rui-Tyler: CARP: Compression-Aware Replacement Policies - “Fully associative software-based cache design,” ISCA 2000. - “The V-way cache: Demand based associativity via global replacement,” ISCA 2005. - “Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,” MICRO 2006.
Jason-Brian: Locality-Aware DRAM and Bandwidth Compression
Hyoseung: Scheduling Real-time Tasks with Bounded Cache and Memory Bus Interference
Joe-Paul: Improving Performance of General Purpose GPU Workloads by Accelerating Highly Divergent Threads - “Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow,” MICRO 2007. - “Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance,” ISCA 2010. - “CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures,” ISCA 2012.
“Thread Block Compaction for Efficient SIMT Control Flow,” HPCA 2011.
“Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,” MICRO 2011.
Hongyi: New enhancement of hash-table aligners
Berkin: Extending Amdahl’s Law for Multiple Multithreaded Tasks
Richard: Automatic Generation of Specialized Parallel CSP Solvers