Table of Contents
Literature Review
The literature survey instructions are here: pdf
Literature survey presentations from past runs of the course can be viewed here (click on “Project + Lit Survey” in the left pane).
Schedule
| November 26th (Mon) | Name(s) |
|---|---|
| Slot 1 | Richard |
| Slot 2 | Berkin |
| Slot 3 | Hongyi |
| Slot 4 | Joe, Paul |
| Slot 5 | Jason, Brian |
| Slot 6 | Rui, Tyler |
| November 28th (Wed) | Name(s) |
|---|---|
| Slot 1 | Samihan |
| Slot 2 | Hyoseung |
| Slot 3 | Donghyuk |
| Slot 4 | Ben |
| Slot 5 | Jamie |
| Slot 6 |
Groups
| Name(s) | Literature Survey Papers |
|---|---|
| Jamie | 1. “Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications”, ASSCC 2006. 2. “RAIDR: Retention-Aware Intelligent DRAM Refresh”, ISCA 2012. 3. “Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM”, HPCA 2006. - More papers to be added. |
| Ben | 1. “The Effectiveness of Multiple Hardware Contexts,” ASPLOS 1994. 2. “Fairness and Throughput in Switch on Event Multithreading,” MICRO 2006. 3. “Fast thread migration via cache working set prediction,” HPCA 2011. - “Cache-Conscious Wavefront Scheduling,” MICRO 2012. |
| Donghyuk | 1. “A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array,” JSSC 2008. 2. “Scalable high performance main memory system using phase-change memory technology,” ISCA 2009. 3. “Automatic CPU-GPU Communication Management and Optimization,” PLDI 2011. 4. “Evaluation of existing architectures in IRAM systems,” ISCA 1997. 5. “Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads,” HPCA 2012. - “All points addressable raster display memory,” IBM Journal of R&D, Vol 28, No. 4, July 1984. |
| Samihan | 1. “Prefetch-Aware Shared Resource Management for Multi-Core Systems,” ISCA 2011. 2. “Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers,” HPCA 2007. 3. “PACMan: Prefetch-Aware Cache Management for High Performance Caching,” MICRO 2011. |
| Rui, Tyler | 1. “Fully associative software-based cache design,” ISCA 2000. 2. “The V-way cache: Demand based associativity via global replacement,” ISCA 2005. 3. “Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,” MICRO 2006. |
| Jason, Brian | 1. “Spatial memory streaming,” ISCA 2006. 2. “Feedback directed prefetching,” ISCA 2007. 3. “Interactions between compression and prefetching in chip multiprocessors,” HPCA 2007. - “Memory-link compression schemes: a value locality perspective,” IEEE Transactions on Computers. |
| Hyoseung | 1. “A Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore System,” PACT 2012. 2. “Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model,” WOSP 1998. 3. “Understanding How Off-Chip Memory Bandwidth Partitioning in Chip Multiprocessors Affects System Performance,” HPCA 2010. 4. “An Analytical Performance Model for Co-Management of Last-Level Cache and Bandwidth Sharing,” MASCOTS 2011. |
| Joe, Paul | 1. “Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow,” MICRO 2007. 2. “Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance,” ISCA 2010. 3. “CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures,” ISCA 2012. - “Thread Block Compaction for Efficient SIMT Control Flow,” HPCA 2011. - “Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,” MICRO 2011. |
| Hongyi | 1. “PatternHunter: faster and more sensitive homology search,” BioInformatics 2002. 2. “Efficient Large-Scale Sequence Comparison by Locality-Sensitive Hashing,” BioInformatics 2001. 3. “Alignment of whole genomes,” Nucl. Acids Res. 1999. 4. “Gapped BLAST and PSI-BLAST: a new generation of protein database search programs,” Nucl. Acids Res. 1997. |
| Berkin | 1. “Modeling critical sections in Amdahl's law and its implications for multicore design,” ISCA 2010. 2. “Amdahl's Law in the Multicore Era,” IEEE Computer 2008. 3. “Dark Silicon and the End of Multicore Scaling,” ISCA 2011. - “Many-Core vs. Many-Thread Machines: Stay Away From the Valley,” CAL 2009. |
| Richard | 1. “Algorithms for Constraint Satisfaction Problems: A Survey,” AI Mag. 1992. 2. “MINION: A Fast Scalable Constraint Solver,” ECAI 2006. 3. “Autotuning a Random Walk Boolean Satisfiability Solver,” ICCS 2011. |
