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reviews [2012/10/12 20:47]
hanbiny 		reviews [2014/09/02 03:31] (current)
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 =====Lecture 16===== =====Lecture 16=====
   * Due Oct 14th - Patel, "Processor-Memory Interconnections for Multiprocessors," ISCA 1979. {{:patel_procmeminterconnect79.pdf|pdf}}   * Due Oct 14th - Patel, "Processor-Memory Interconnections for Multiprocessors," ISCA 1979. {{:patel_procmeminterconnect79.pdf|pdf}}
 +
   * Due Oct 16th - Moscibroda and Mutlu, "A Case for Bufferless Routing in On-Chip Networks," ISCA 2009. {{:moscibroda09.pdf|pdf}}   * Due Oct 16th - Moscibroda and Mutlu, "A Case for Bufferless Routing in On-Chip Networks," ISCA 2009. {{:moscibroda09.pdf|pdf}}
 +
 +=====Lecture 20=====
 +  * Due Oct 28th - Das et al., "Aergia: Exploiting Packet Latency Slack in On-Chip Networks," ISCA 2010. {{:das_aergia.pdf|pdf}}
 +  * Due Oct 28th - Dennis and Misunas, "A preliminary architecture for a basic data flow processor," ISCA 1974. {{:dennis74.pdf|pdf}}
 +
 +  * Due Oct 30th - Arvind and Nikhil, "Executing a program on the MIT tagged-token dataflow architecture," IEEE TC 1990. {{:arvind90.pdf|pdf}}
 +
 +=====Lecture 21=====
 +  * Due Nov 1st - Patt et al., "HPS, a new microarchitecture: rationale and introduction," MICRO 1985. {{:patt85.pdf|pdf}}
 +  * Due Nov 1st - Patt et al., "Critical issues regarding HPS, a high performance microarchitecture," MICRO 1985. {{:patt85-hpsissues.pdf|pdf}}
 +
 +=====Lecture 23=====
 +  * Due Nov 4th - Kung, “Why Systolic Architectures?,” IEEE Computer 1982. {{:kung_systolic82.pdf|pdf}}
 +
 +=====Lecture 24=====
 +  * Due Nov 13th - Mutlu and Moscibroda, “Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems,” ISCA 2008. {{:mutlu08-parbs.pdf|pdf}}
 +  * Due Nov 13th - Kim et al., “Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,” MICRO 2010. {{:kim10-tcm.pdf|pdf}}
 +
 +  * Due Nov 15th - Ebrahimi et al., “Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems,” ASPLOS 2010. {{:ebrahimi_throttle10.pdf|pdf}}
 +  * Due Nov 15th - Muralidhara et al., “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning,” MICRO 2011. {{:mcp_micro2011.pdf|pdf}}

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