Readings

Post your paper reviews for the papers marked [Review Required] on the paper review site . The expectations for these reviews are described in Recitation 1. You can view reviews by other students only after the deadline.

1. Onur Mutlu and Lavanya Subramanian, Research Problems and Opportunities in Memory Systems, Invited Article in Supercomputing Frontiers and Innovations (SUPERFRI), 2015. [Review Required]
2. Onur Mutlu, Rethinking the Systems We Design, Technical talk at A Computer Architecture Workshop: Visions for the Future (Celebrating Yale@75) (YALE@75), Austin, TX, September 2014 [Review Required]
3. Junwhan Ahn et al., A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015. [Optional]
4. Vivek Seshadri et al., Fast Bulk Bitwise AND and OR in DRAM, IEEE Computer Architecture Letters (CAL), April 2015. [Review Required]

1. Smith, Task of the Referee, IEEE Computer 1990.
2. Hill and McKinley, Notes on Constructive and Positive Reviewing
3. Thomas Moscibroda and Onur Mutlu, Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007.

1. Ahn et al., A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015. [Review Required]
2. Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, GPUs and the Future of Parallel Computing, IEEE Micro 2011. [Review Required]
3. Jeffrey D. Ullman, Experiments as Research Validation: Have We Gone Too Far?, CACM 2015. [Review Required]
4. Nandita Vijaykumar et al., A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps, ISCA 2015. [Review Required]
5. Yu Cai et al., Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation, DSN 2015. [Optional]

1. Moore, Cramming more components onto integrated circuits, Electronics Magazine, 1965.
2. Kuhn, The structure of scientific revolutions, 1962.
3. Hill and McKinley, Notes on Constructive and Positive Reviewing
4. Levin and Redell, How (and how not) to write a good systems paper, OSR 1983.
5. Jones, How to Write a Great Research Paper
6. Fong, How to Write a CS Research Paper: A Bibliography
7. Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015.
8. Nickolls and Dally, The GPU Computing Era , IEEE Micro 2010.
9. Schulte et al., Achieving Exascale Capabilities through Heterogeneous Computing , IEEE Micro 2015.
10. Michael Mitzenmacher, Theory Without Experiments: Have We Gone Too Far?, CACM 2015.
11. Kim et al., Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
12. Meza et al., Enabling Efficient and Scalable Hybrid Memories, IEEE Comp. Arch. Letters, 2012.
13. Yoon, Meza et al., Row Buffer Locality Aware Caching Policies for Hybrid Memories, ICCD 2012.
14. Subramanian et al., MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,, HPCA 2013
15. Lui et al., Flikker: Saving DRAM Refresh-power through Critical Data Partitioning, ASPLOS 2011.
16. Lefurgy, et al., Energy Management for Commercial Servers, IEEE Computer 2003.
17. Larus, Spending Moore's Dividend

1. Cai et al., Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation, DSN 2015. [Review Required]
2. Lee et al., Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009 [Review Required]
3. Joao et al., Bottleneck Identification and Scheduling in Multithreaded Applications, ASPLOS 2012. [Review Required]
4. Ebrahimi et al., Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010. [Optional]

• Cai et al., Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015
• Lee et al., Phase Change Technology and the Future of Main Memory, IEEE Micro 2010
• Suleman et al., Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures, ASPLOS 2009
• Kang et al., Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling, Memory Form 2014
• Seshadri et al., Fast Bulk Bitwise AND and OR in DRAM, IEEE Computer Architecture Letters (CAL), April 2015.
• Seshadri et al., RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization , MICRO 2013
• Ahn et al., A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015.
• Loh et al., 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA 2008.
• Dennis et al., A Preliminary Architecture for a Basic Data Flow Processor, ISCA 1974.

• T. Yeh and Y. Patt Two-Level Adaptive Training Branch Prediction, Intl. Symposium on Microarchitecture, November 1991. MICRO Test of Time Award Winner (after 24 years).
• Kessler, R. E., The Alpha 21264 Microprocessor, IEEE Micro, March/April 1999, pp. 24-36
• McFarling, S., Combining Branch Predictors, DEC WRL Technical Report, TN-36, June 1993
• Smith and Sohi, The Microarchitecture of Superscalar Processors, Proceedings of the IEEE, 1995.
• Evers et al., An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work, ISCA 1998
• Chang et al., Branch classification: a new mechanism for improving branch predictor performance, MICRO 1994
• Sprangle et al., The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference, ISCA 1997.
• Seznec, An optimized 2bcgskew branch predictor, IRISA Tech Report 1993.
• Michaud, Trading conflict and capacity aliasing in conditional branch predictors, ISCA 1997
• Lee et al., The bi-mode branch predictor, MICRO 1997.
• Eden and Mudge, The YAGS branch prediction scheme, MICRO 1998.
• Seznec et al., Design tradeoffs for the Alpha EV8 conditional branch predictor, ISCA 2002.
• Chappell et al., Simultaneous Subordinate Microthreading (SSMT), ISCA 1999.
• Seznec, Analysis of the O-Geometric History Length branch predictor, ISCA 2005
• Gochman et al., The Intel Pentium M Processor: Microarchitecture and Performance, Intel Technology Journal, May 2003
• Jimenez and Lin, Dynamic Branch Prediction with Perceptrons, HPCA 2001
• Rosenblatt, Principles of Neurodynamics: Perceptrons and the Theory of Brain Mechanisms, 1962
• Seznec and Michaud, A case for (partially) tagged Geometric History Length Branch Prediction, JILP 2006.
• Andre Seznec, TAGE-SC-L branch predictors, CBP 2014
• Chappell et al., Difficult-Path Branch Prediction Using Subordinate Microthreads, ISCA 2002.
• Jacobsen et al., Assigning Confidence to Conditional Branch Predictions, MICRO 1996.
• Manne et al., Pipeline Gating: Speculation Control for Energy Reduction, ISCA 1998
• Pettis and Hansen, Profile Guided Code Positioning, PLDI 1990.
• Hwu et al., The Superblock: An effective technique for VLIW and superscalar compilation,” Journal of Supercomputing, 1993.
• Rotenberg et al., Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching, MICRO 1996.
• Patel et al., Critical Issues Regarding the Trace Cache Fetch Mechanism, Umich TR, 1997.
• A. Peleg, U. Weiser, Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line, United States Patent No. 5,381,533, Jan 10, 1995.

• Eiman Ebrahimi et. al.,  Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010 [Review Required]
• Rachata Ausavarungnirun et. al., Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance, PACT 2015 [Review Required]
• Donghyuk Lee et. al., Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013 [Review Required]
• Justin Meza et. al., A Large-Scale Study of Flash Memory Errors in the Field, SIGMETRICS 2015 [Optional]

• Kevin Chang et. al., HAT: Heterogeneous Adaptive Throttling for On-Chip Networks, SBAC-PAD 2012
• Wilson W. L. Fung et. al., Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow, MICRO 2007
• Donghyuk Lee et. al., Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015
• Justin Meza et. al.,  Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field, DSN 2015
• Junwhan Ahn et al., A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015.
• Vivek Seshadri et al., Fast Bulk Bitwise AND and OR in DRAM, IEEE Computer Architecture Letters (CAL), April 2015.
• Seshadri et al., RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization , MICRO 2013
• Junwhan Ahn et. al., PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA 2015.
• Liu et. al., An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms, ISCA 2013.
• Khan et. al., The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study, SIGMETRICS 2014.
• Luo et. al., Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost, DSN 2014
• Kim et al., Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
• Cai et. al. Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation. ICCD 2013
• Cai et. al., Error Analysis and Retention-Aware Error Management for NAND Flash Memory, Intel Technology Journal 2013
• Cai et. al., Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories, SIGMETRICS 2014
• Lee et. al., Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015
• Qureshi et al. AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems, DSN 2015
• Lee et al., Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009
• Yoon, Meza et al., Row Buffer Locality Aware Caching Policies for Hybrid Memories, ICCD 2012
• Meza et. al., Enabling Efficient and Scalable Hybrid Memories, IEEE Comp. Arch. Letters, 2012

• Yoon et. al., Virtualized and Flexible ECC for Main Memory, ASPLOS 2010
• Cai et al., Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015
• Raoux et. al., Phase-change random access memory: A scalable technology, IBM JRD 2008
• Qureshi et. al., Scalable High Performance Main Memory System Using Phase-Change Memory Technology, ISCA 2009

• Onur Mutlu and Lavanya Subramanian, Research Problems and Opportunities in Memory Systems, Invited Article in Supercomputing Frontiers and Innovations (SUPERFRI), 2015.
• Lee et al., Phase Change Technology and the Future of Main Memory, IEEE Micro 2010
• Yoongu Kim et. al. Ramulator: A Fast and Extensible DRAM Simulator, IEEE Computer Architecture Letters, May 2015.
• Yoongu Kim et al., Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
• Seaborn et.al., Exploiting the DRAM rowhammer bug to gain kernel privileges, 2015
• Donghyuk Lee et. al., Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013
• Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.
• Liu et. al., An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms, ISCA 2013.
• Khan et. al., The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study, SIGMETRICS 2014.
• Lee et. al., Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015
• Qureshi et al. AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems, DSN 2015
• Yoon, Meza et al., Row Buffer Locality Aware Caching Policies for Hybrid Memories, ICCD 2012
• Meza et. al., Enabling Efficient and Scalable Hybrid Memories, IEEE Comp. Arch. Letters, 2012
• Luo et. al., Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost, DSN 2014
• Subramanian et al., The Application Slowdown Model, MICRO 2015.
• Subramanian et al., MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,, HPCA 2013
• Wilkes, Slave Memories and Dynamic Storage Allocation, IEEE Trans. On Electronic Computers, 1965.
• Lee et al., Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009
• Yoongu Kim et al., A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM, ISCA 2012
• Rau, Pseudo-randomly Interleaved Memory, ISCA 1991
• Lee et al., DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems, HPS Technical Report, April 2010.
• Ipek et al., Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008
• J. Zhao et al., FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems, MICRO 2014.
• M. Qureshi et al., Scalable high performance main memory system using phase-change memory technology, ISCA 2009.

• Justin Meza et al., A Large-Scale Study of Flash Memory Errors in the Field, SIGMETRICS 2015 [Review Required]
• Yu Cai et al., Error Analysis and Retention-Aware Error Management for NAND Flash Memory, Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May 2013. [Review Required]
• Edmund B. Nightingale et al, Cycles, cells and platters: an empirical analysis of hardware failures on a million consumer PCs, Eurosys 2011. [Review Required]
• Loh et al., 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA 2008. [Optional]
• Black et al., Die Stacking (3D) Microarchitecture, MICRO 2006. [Optional]

• Ipek et al., Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008
• J. Zhao et al., FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems, MICRO 2014.
• M. Qureshi et al., Scalable high performance main memory system using phase-change memory technology, ISCA 2009.
• Yoongu Kim et. al. Ramulator: A Fast and Extensible DRAM Simulator, IEEE Computer Architecture Letters, May 2015.
• Justin Meza et. al.,  Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field, DSN 2015
• Yoon, Meza et al., Row Buffer Locality Aware Caching Policies for Hybrid Memories, ICCD 2012
• Meza et. al., Enabling Efficient and Scalable Hybrid Memories, IEEE Comp. Arch. Letters, 2012
• Qureshi et. al., Scalable High Performance Main Memory System Using Phase-Change Memory Technology, ISCA 2009
• Kultursay et al., Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative, ISPASS 2013.
• Meza et al., A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory, WEED 2013.

• Loh et al., 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA 2008. [Required]
• Black et al., Die Stacking (3D) Microarchitecture, MICRO 2006. [Required]
• Yoon et. al., Virtualized and Flexible ECC for Main Memory, ASPLOS 2010 [Required]

• Perais et al., EOLE: Paving the Way for an Effective Implementation of Value Prediction, ISCA 2014. [Required]
• Reinhardt et al., Transient fault detection via simultaneous multithreading, ISCA 2000. [Required]
• Constantinides et al. Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation, MICRO 2007. [Required]

• Mike O'Connor, High-bandwidth, Energy-efficient DRAM Architectures for GPU Systems , CALCM Talk [Required]

• Mutlu et al., Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, ISCA 2008.
• Muralidhara et al., Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011.
• Ebrahimi et al., Parallel Application Memory Scheduling, MICRO 2011.
• Wang et al., A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters,VEE 2015.
• Moscibroda et al., Memory Performance Attacks, USENIX Security 2007.
• Mutlu et. al., Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, MICRO 2007.
• Kim et al., ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,HPCA 2010.
• Kim et al.,Thread Cluster Memory Scheduling, MICRO 2010.
• Ebrahimi et. al.,  Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010

• Moscibroda et al., A Case for Bufferless Routing in On-Chip Networks , ISCA 2009
• Das et al., Application-Aware Prioritization Mechanisms for On-Chip Networks, MICRO 2009

• Joao et al., Bottleneck Identification and Scheduling in Multithreaded Applications, ASPLOS 2012.
• Suleman et al., Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures, ASPLOS 2009
• Gorchowski et al., Best of Both Latency and Throughput, ICCD 2004.
• Meza et al., Enabling Efficient and Scalable Hybrid Memories, IEEE Comp. Arch. Letters, 2012.
• Yoon, Meza et al., Row Buffer Locality Aware Caching Policies for Hybrid Memories, ICCD 2012.
• Kim et al.,Thread Cluster Memory Scheduling, MICRO 2010.
• Tendler et al., POWER4 system microarchitecture, IBM J R&D, 2002.
• Kalla et al., IBM Power5 Chip: A Dual-Core Multithreaded Processor, IEEE Micro 2004.
• Konngetira et al., Niagara: A 32-Way Multithreaded SPARC Processor, IEEE Micro 2005
• Luo et. al., Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost, DSN 2014
• Donghyuk Lee et. al., Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013

1. Kubaib et al., MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP, MICRO 2012

1. Mutlu et al., Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, MICRO 2008

1. Hirata et al., An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, ISCA 1992.
2. Tullsen et al., Simultaneous Multithreading: Maximizing On-Chip Parallelism, ISCA 1996.
3. Levin and Redell, How (and How Not) to Write a Good Systems Paper, Operating Systems Review 1983.

1. Peyton-Jones, How to give a good research talk, How to write a great research paper, How to write a good research proposal
2. Hamming, You and Your Research, 1986.
3. Bransford, J.D., & Johnson, M.K., Contextual prerequisites for understanding: Some investigations of comprehension and recall, Journal of Verbal Learning and Verbal Behavior, 11, 717-726.