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| * Astronautics ZS-1 | * Astronautics ZS-1 | ||
| * Loop unrolling | * Loop unrolling | ||
| + | |||
| + | ==== Lecture 27 ==== | ||
| + | VLIW | ||
| + | |||
| + | * Each VLIW instruction - a bundle of independent instructions (identified by compiler) | ||
| + | * Each instruction bundle executed by hardware in lockstep | ||
| + | * Commercial VLIW machines | ||
| + | - TIC6000, Trimedia, STMicro | ||
| + | * Intel IA-64 - Partially VLIW | ||
| + | * Encoding VLIW NOPs | ||
| + | * Static Instruction Scheduling for VLIW | ||
| + | * Code motion - Safety & Legality | ||
| + | * Trace scheduling | ||
| + | * List scheduling | ||
| + | * Super block scheduling | ||
| + | * Hyperblock scheduling | ||
| + | * The Intel IA-64 architecture | ||
| + | - No lock step execution of a bundle | ||
| + | - Specify dependencies between instructions within a bundle | ||
| + | - Template bits | ||
| + | * What hinder static mode motion? | ||
| + | - Exceptions | ||
| + | - Loads/Stores | ||
