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buzzwords [2010/11/29 21:57] lsubrama |
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| Control Flow - III & Concurrency | Control Flow - III & Concurrency | ||
| - | * | + | * Predicated Execution |
| + | - Predication decisions at the compiler | ||
| + | - Rename stage modifications | ||
| + | * Limitations of predication | ||
| + | - Adaptivity | ||
| + | - Complex Control Flow Graphs | ||
| + | - ISA support | ||
| + | * Wish branches | ||
| + | - Wish jump/join | ||
| + | - Wish loop | ||
| + | * Wish branches vs Predicated Execution | ||
| + | * Wish branches vs Branch prediction | ||
| + | * Diverge-Merge Processor | ||
| + | * Dynamic-Hammock | ||
| + | * Multi-path Execution | ||
| + | * Research issues in control flow handling | ||
| + | - Hardware/software cooperation | ||
| + | - Fetch gating | ||
| + | - Recycling useful work done on wrong path | ||
| + | Concurrency | ||
| + | * Classification of machines | ||
| + | - SISD | ||
| + | - SIMD | ||
| + | - MIMD | ||
| + | * Decoupled Access/Execute | ||
| + | * Astronautics ZS-1 | ||
| + | * Loop unrolling | ||
| + | |||
| + | ==== Lecture 27 ==== | ||
| + | VLIW | ||
| + | |||
| + | * Each VLIW instruction - a bundle of independent instructions (identified by compiler) | ||
| + | * Each instruction bundle executed by hardware in lockstep | ||
| + | * Commercial VLIW machines | ||
| + | - TIC6000, Trimedia, STMicro | ||
| + | * Intel IA-64 - Partially VLIW | ||
| + | * Encoding VLIW NOPs | ||
| + | * Static Instruction Scheduling for VLIW | ||
| + | * Code motion - Safety & Legality | ||
| + | * Trace scheduling | ||
| + | * List scheduling | ||
| + | * Super block scheduling | ||
| + | * Hyperblock scheduling | ||
| + | * The Intel IA-64 architecture | ||
| + | - No lock step execution of a bundle | ||
| + | - Specify dependencies between instructions within a bundle | ||
| + | - Template bits | ||
| + | * What hinder static mode motion? | ||
| + | - Exceptions | ||
| + | - Loads/Stores | ||
